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347 lines
12 KiB
C++
347 lines
12 KiB
C++
//===-- RegAllocBasic.cpp - basic register allocator ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RABasic function pass, which provides a minimal
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// implementation of the basic register allocator.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "LiveIntervalUnion.h"
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#include "RegAllocBase.h"
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#include "RenderMachineFunction.h"
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#include "Spiller.h"
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#include "VirtRegRewriter.h"
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#include "llvm/Function.h"
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#include "llvm/PassAnalysisSupport.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <vector>
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#include <queue>
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using namespace llvm;
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static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
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createBasicRegisterAllocator);
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namespace {
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/// RABasic provides a minimal implementation of the basic register allocation
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/// algorithm. It prioritizes live virtual registers by spill weight and spills
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/// whenever a register is unavailable. This is not practical in production but
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/// provides a useful baseline both for measuring other allocators and comparing
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/// the speed of the basic algorithm against other styles of allocators.
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class RABasic : public MachineFunctionPass, public RegAllocBase
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{
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// context
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MachineFunction *mf_;
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const TargetMachine *tm_;
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MachineRegisterInfo *mri_;
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// analyses
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LiveStacks *ls_;
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RenderMachineFunction *rmf_;
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// state
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std::auto_ptr<Spiller> spiller_;
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public:
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RABasic();
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/// Return the pass name.
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virtual const char* getPassName() const {
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return "Basic Register Allocator";
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}
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/// RABasic analysis usage.
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virtual void getAnalysisUsage(AnalysisUsage &au) const;
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virtual void releaseMemory();
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virtual unsigned selectOrSplit(LiveInterval &lvr,
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SmallVectorImpl<LiveInterval*> &splitLVRs);
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/// Perform register allocation.
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virtual bool runOnMachineFunction(MachineFunction &mf);
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static char ID;
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};
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char RABasic::ID = 0;
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} // end anonymous namespace
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// We should not need to publish the initializer as long as no other passes
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// require RABasic.
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#if 0 // disable INITIALIZE_PASS
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INITIALIZE_PASS_BEGIN(RABasic, "basic-regalloc",
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"Basic Register Allocator", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
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INITIALIZE_AG_DEPENDENCY(RegisterCoalescer)
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INITIALIZE_PASS_DEPENDENCY(CalculateSpillWeights)
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INITIALIZE_PASS_DEPENDENCY(LiveStacks)
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INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
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INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
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#ifndef NDEBUG
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INITIALIZE_PASS_DEPENDENCY(RenderMachineFunction)
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#endif
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INITIALIZE_PASS_END(RABasic, "basic-regalloc",
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"Basic Register Allocator", false, false)
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#endif // disable INITIALIZE_PASS
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RABasic::RABasic(): MachineFunctionPass(ID) {
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initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
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initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
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initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
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initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
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initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
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initializeLiveStacksPass(*PassRegistry::getPassRegistry());
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initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
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initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
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initializeRenderMachineFunctionPass(*PassRegistry::getPassRegistry());
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}
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void RABasic::getAnalysisUsage(AnalysisUsage &au) const {
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au.setPreservesCFG();
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au.addRequired<LiveIntervals>();
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au.addPreserved<SlotIndexes>();
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if (StrongPHIElim)
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au.addRequiredID(StrongPHIEliminationID);
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au.addRequiredTransitive<RegisterCoalescer>();
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au.addRequired<CalculateSpillWeights>();
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au.addRequired<LiveStacks>();
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au.addPreserved<LiveStacks>();
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au.addRequired<MachineLoopInfo>();
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au.addPreserved<MachineLoopInfo>();
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au.addRequired<VirtRegMap>();
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au.addPreserved<VirtRegMap>();
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DEBUG(au.addRequired<RenderMachineFunction>());
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MachineFunctionPass::getAnalysisUsage(au);
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}
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void RABasic::releaseMemory() {
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spiller_.reset(0);
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RegAllocBase::releaseMemory();
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}
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//===----------------------------------------------------------------------===//
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// RegAllocBase Implementation
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//===----------------------------------------------------------------------===//
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// Instantiate a LiveIntervalUnion for each physical register.
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void RegAllocBase::LIUArray::init(unsigned nRegs) {
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array_.reset(new LiveIntervalUnion[nRegs]);
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nRegs_ = nRegs;
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for (unsigned pr = 0; pr < nRegs; ++pr) {
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array_[pr].init(pr);
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}
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}
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void RegAllocBase::init(const TargetRegisterInfo &tri, VirtRegMap &vrm,
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LiveIntervals &lis) {
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tri_ = &tri;
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vrm_ = &vrm;
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lis_ = &lis;
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physReg2liu_.init(tri_->getNumRegs());
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}
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void RegAllocBase::LIUArray::clear() {
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nRegs_ = 0;
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array_.reset(0);
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}
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void RegAllocBase::releaseMemory() {
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physReg2liu_.clear();
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}
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namespace llvm {
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/// This class defines a queue of live virtual registers prioritized by spill
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/// weight. The heaviest vreg is popped first.
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///
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/// Currently, this is trivial wrapper that gives us an opaque type in the
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/// header, but we may later give it a virtual interface for register allocators
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/// to override the priority queue comparator.
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class LiveVirtRegQueue {
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typedef std::priority_queue
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<LiveInterval*, std::vector<LiveInterval*>, LessSpillWeightPriority> PQ;
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PQ pq_;
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public:
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// Is the queue empty?
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bool empty() { return pq_.empty(); }
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// Get the highest priority lvr (top + pop)
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LiveInterval *get() {
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LiveInterval *lvr = pq_.top();
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pq_.pop();
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return lvr;
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}
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// Add this lvr to the queue
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void push(LiveInterval *lvr) {
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pq_.push(lvr);
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}
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};
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} // end namespace llvm
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// Visit all the live virtual registers. If they are already assigned to a
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// physical register, unify them with the corresponding LiveIntervalUnion,
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// otherwise push them on the priority queue for later assignment.
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void RegAllocBase::seedLiveVirtRegs(LiveVirtRegQueue &lvrQ) {
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for (LiveIntervals::iterator liItr = lis_->begin(), liEnd = lis_->end();
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liItr != liEnd; ++liItr) {
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unsigned reg = liItr->first;
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LiveInterval &li = *liItr->second;
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if (TargetRegisterInfo::isPhysicalRegister(reg)) {
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physReg2liu_[reg].unify(li);
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}
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else {
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lvrQ.push(&li);
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}
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}
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}
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// Top-level driver to manage the queue of unassigned LiveVirtRegs and call the
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// selectOrSplit implementation.
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void RegAllocBase::allocatePhysRegs() {
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LiveVirtRegQueue lvrQ;
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seedLiveVirtRegs(lvrQ);
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while (!lvrQ.empty()) {
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LiveInterval *lvr = lvrQ.get();
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typedef SmallVector<LiveInterval*, 4> LVRVec;
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LVRVec splitLVRs;
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unsigned availablePhysReg = selectOrSplit(*lvr, splitLVRs);
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if (availablePhysReg) {
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assert(splitLVRs.empty() && "inconsistent splitting");
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assert(!vrm_->hasPhys(lvr->reg) && "duplicate vreg in interval unions");
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vrm_->assignVirt2Phys(lvr->reg, availablePhysReg);
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physReg2liu_[availablePhysReg].unify(*lvr);
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}
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else {
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for (LVRVec::iterator lvrI = splitLVRs.begin(), lvrEnd = splitLVRs.end();
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lvrI != lvrEnd; ++lvrI) {
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assert(TargetRegisterInfo::isVirtualRegister((*lvrI)->reg) &&
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"expect split value in virtual register");
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lvrQ.push(*lvrI);
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}
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}
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}
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}
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// Check if this live virtual reg interferes with a physical register. If not,
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// then check for interference on each register that aliases with the physical
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// register.
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bool RegAllocBase::checkPhysRegInterference(LiveIntervalUnion::Query &query,
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unsigned preg) {
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if (query.checkInterference())
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return true;
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for (const unsigned *asI = tri_->getAliasSet(preg); *asI; ++asI) {
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// We assume it's very unlikely for a register in the alias set to also be
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// in the original register class. So we don't bother caching the
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// interference.
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LiveIntervalUnion::Query subQuery(query.lvr(), physReg2liu_[*asI] );
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if (subQuery.checkInterference())
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return true;
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}
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return false;
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}
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//===----------------------------------------------------------------------===//
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// RABasic Implementation
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//===----------------------------------------------------------------------===//
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// Driver for the register assignment and splitting heuristics.
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// Manages iteration over the LiveIntervalUnions.
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//
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// Minimal implementation of register assignment and splitting--spills whenever
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// we run out of registers.
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//
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// selectOrSplit can only be called once per live virtual register. We then do a
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// single interference test for each register the correct class until we find an
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// available register. So, the number of interference tests in the worst case is
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// |vregs| * |machineregs|. And since the number of interference tests is
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// minimal, there is no value in caching them.
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unsigned RABasic::selectOrSplit(LiveInterval &lvr,
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SmallVectorImpl<LiveInterval*> &splitLVRs) {
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// Check for an available reg in this class.
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const TargetRegisterClass *trc = mri_->getRegClass(lvr.reg);
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for (TargetRegisterClass::iterator trcI = trc->allocation_order_begin(*mf_),
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trcEnd = trc->allocation_order_end(*mf_);
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trcI != trcEnd; ++trcI) {
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unsigned preg = *trcI;
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LiveIntervalUnion::Query query(lvr, physReg2liu_[preg]);
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if (!checkPhysRegInterference(query, preg)) {
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DEBUG(dbgs() << "\tallocating: " << tri_->getName(preg) << lvr << '\n');
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return preg;
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}
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}
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DEBUG(dbgs() << "\tspilling: " << lvr << '\n');
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SmallVector<LiveInterval*, 1> spillIs; // ignored
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spiller_->spill(&lvr, splitLVRs, spillIs);
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// FIXME: update LiveStacks
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return 0;
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}
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bool RABasic::runOnMachineFunction(MachineFunction &mf) {
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DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
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<< "********** Function: "
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<< ((Value*)mf.getFunction())->getName() << '\n');
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mf_ = &mf;
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tm_ = &mf.getTarget();
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mri_ = &mf.getRegInfo();
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DEBUG(rmf_ = &getAnalysis<RenderMachineFunction>());
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RegAllocBase::init(*tm_->getRegisterInfo(), getAnalysis<VirtRegMap>(),
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getAnalysis<LiveIntervals>());
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spiller_.reset(createSpiller(*this, *mf_, *vrm_));
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allocatePhysRegs();
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// Diagnostic output before rewriting
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DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm_ << "\n");
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// optional HTML output
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DEBUG(rmf_->renderMachineFunction("After basic register allocation.", vrm_));
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// Run rewriter
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std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
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rewriter->runOnMachineFunction(*mf_, *vrm_, lis_);
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// The pass output is in VirtRegMap. Release all the transient data.
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releaseMemory();
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return true;
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}
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FunctionPass* llvm::createBasicRegisterAllocator()
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{
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return new RABasic();
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}
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