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b0d4492aa1
Unified EmitTextAttribute for both Asm and Obj emission (.cpu only) Added necessary cortex-A8 related attrs for codegen compat tests. llvm-svn: 124995
132 lines
4.6 KiB
C++
132 lines
4.6 KiB
C++
//===-------- ARMBuildAttrs.h - ARM Build Attributes ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains enumerations and support routines for ARM build attributes
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// as defined in ARM ABI addenda document (ABI release 2.08).
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//
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//===----------------------------------------------------------------------===//
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#ifndef __TARGET_ARMBUILDATTRS_H__
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#define __TARGET_ARMBUILDATTRS_H__
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namespace ARMBuildAttrs {
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enum SpecialAttr {
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// This is for the .cpu asm attr. It translates into one or more
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// AttrType (below) entries in the .ARM.attributes section in the ELF.
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SEL_CPU
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};
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enum AttrType {
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// Rest correspond to ELF/.ARM.attributes
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File = 1,
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Section = 2,
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Symbol = 3,
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CPU_raw_name = 4,
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CPU_name = 5,
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CPU_arch = 6,
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CPU_arch_profile = 7,
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ARM_ISA_use = 8,
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THUMB_ISA_use = 9,
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VFP_arch = 10,
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WMMX_arch = 11,
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Advanced_SIMD_arch = 12,
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PCS_config = 13,
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ABI_PCS_R9_use = 14,
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ABI_PCS_RW_data = 15,
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ABI_PCS_RO_data = 16,
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ABI_PCS_GOT_use = 17,
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ABI_PCS_wchar_t = 18,
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ABI_FP_rounding = 19,
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ABI_FP_denormal = 20,
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ABI_FP_exceptions = 21,
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ABI_FP_user_exceptions = 22,
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ABI_FP_number_model = 23,
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ABI_align8_needed = 24,
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ABI_align8_preserved = 25,
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ABI_enum_size = 26,
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ABI_HardFP_use = 27,
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ABI_VFP_args = 28,
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ABI_WMMX_args = 29,
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ABI_optimization_goals = 30,
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ABI_FP_optimization_goals = 31,
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compatibility = 32,
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CPU_unaligned_access = 34,
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VFP_HP_extension = 36,
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ABI_FP_16bit_format = 38,
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MPextension_use = 42, // was 70, 2.08 ABI
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DIV_use = 44,
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nodefaults = 64,
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also_compatible_with = 65,
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T2EE_use = 66,
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conformance = 67,
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Virtualization_use = 68,
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MPextension_use_old = 70
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};
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// Magic numbers for .ARM.attributes
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enum AttrMagic {
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Format_Version = 0x41
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};
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// Legal Values for CPU_arch, (=6), uleb128
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enum CPUArch {
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Pre_v4 = 0,
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v4 = 1, // e.g. SA110
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v4T = 2, // e.g. ARM7TDMI
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v5T = 3, // e.g. ARM9TDMI
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v5TE = 4, // e.g. ARM946E_S
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v5TEJ = 5, // e.g. ARM926EJ_S
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v6 = 6, // e.g. ARM1136J_S
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v6KZ = 7, // e.g. ARM1176JZ_S
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v6T2 = 8, // e.g. ARM1156T2F_S
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v6K = 9, // e.g. ARM1136J_S
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v7 = 10, // e.g. Cortex A8, Cortex M3
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v6_M = 11, // e.g. Cortex M1
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v6S_M = 12, // v6_M with the System extensions
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v7E_M = 13 // v7_M with DSP extensions
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};
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enum CPUArchProfile { // (=7), uleb128
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Not_Applicable = 0, // pre v7, or cross-profile code
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ApplicationProfile = (0x41), // 'A' (e.g. for Cortex A8)
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RealTimeProfile = (0x52), // 'R' (e.g. for Cortex R4)
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MicroControllerProfile = (0x4D), // 'M' (e.g. for Cortex M3)
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SystemProfile = (0x53) // 'S' Application or real-time profile
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};
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// The following have a lot of common use cases
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enum {
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//ARMISAUse (=8), uleb128 and THUMBISAUse (=9), uleb128
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Not_Allowed = 0,
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Allowed = 1,
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// FP_arch (=10), uleb128 (formerly Tag_VFP_arch = 10)
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AllowFPv2 = 2, // v2 FP ISA permitted (implies use of the v1 FP ISA)
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AllowFPv3A = 3, // v3 FP ISA permitted (implies use of the v2 FP ISA)
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AllowFPv3B = 4, // v3 FP ISA permitted, but only D0-D15, S0-S31
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AllowFPv4A = 5, // v4 FP ISA permitted (implies use of v3 FP ISA)
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AllowFPv4B = 6, // v4 FP ISA was permitted, but only D0-D15, S0-S31
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// Tag_WMMX_arch, (=11), uleb128
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AllowThumb32 = 2, // 32-bit Thumb (implies 16-bit instructions)
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// Tag_WMMX_arch, (=11), uleb128
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AllowWMMXv1 = 2, // The user permitted this entity to use WMMX v2
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// Tag_ABI_FP_denormal, (=20), uleb128
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PreserveFPSign = 2, // sign when flushed-to-zero is preserved
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// Tag_ABI_FP_number_model, (=23), uleb128
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AllowRTABI = 2, // numbers, infinities, and one quiet NaN (see [RTABI])
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AllowIEE754 = 3 // this code to use all the IEEE 754-defined FP encodings
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};
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}
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#endif // __TARGET_ARMBUILDATTRS_H__
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