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llvm-mirror/lib/Target/AArch64
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Aditya Nandakumar c0251c505e [GISel]: Add GISelKnownBits analysis 
https://reviews.llvm.org/D65698

This adds a KnownBits analysis pass for GISel. This was done as a
pass (compared to static functions) so that we can add other features
such as caching queries(within a pass and across passes) in the future.
This patch only adds the basic pass boiler plate, and implements a lazy
non caching knownbits implementation (ported from SelectionDAG). I've
also hooked up the AArch64PreLegalizerCombiner pass to use this - there
should be no compile time regression as the analysis is lazy.

llvm-svn: 368065
2019-08-06 17:18:29 +00:00
..
AsmParser [AArch64][SVE2] Rename bitperm feature to sve2-bitperm 2019-07-26 15:57:50 +00:00
Disassembler Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
MCTargetDesc MC: AArch64: Add support for prel_g* relocation specifiers. 2019-07-18 16:54:33 +00:00
TargetInfo Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
Utils AArch64: Add a tagged-globals backend feature. 2019-07-31 20:14:19 +00:00
AArch64.h Basic MTE stack tagging instrumentation. 2019-07-17 19:24:12 +00:00
AArch64.td AArch64: Add a tagged-globals backend feature. 2019-07-31 20:14:19 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
AArch64AsmPrinter.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
AArch64BranchTargets.cpp
AArch64CallingConvention.cpp
AArch64CallingConvention.h
AArch64CallingConvention.td [AArch64] Implement initial SVE calling convention support 2019-08-05 13:44:10 +00:00
AArch64CallLowering.cpp [GlobalISel][CallLowering] Rename isArgumentHandler() -> isIncomingArgumentHandler() 2019-08-05 23:05:28 +00:00
AArch64CallLowering.h [GISel] Address review feedback on passing MD_callees to lowerCall. 2019-07-31 20:34:05 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64CompressJumpTables.cpp [AArch64] Fix scan-build null/uninitialized pointer warnings. NFCI. 2019-05-08 16:27:24 +00:00
AArch64CondBrTuning.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
AArch64ConditionalCompares.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
AArch64ExpandImm.cpp
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp [AArch64] NFC: Add generic StackOffset to describe scalable offsets. 2019-08-06 13:06:40 +00:00
AArch64FalkorHWPFFix.cpp CodeGen: Introduce a class for registers 2019-06-24 15:50:29 +00:00
AArch64FastISel.cpp SelectionDAG, MI, AArch64: Widen target flags fields/arguments from unsigned char to unsigned. 2019-07-31 20:14:09 +00:00
AArch64FrameLowering.cpp [AArch64] NFC: Add generic StackOffset to describe scalable offsets. 2019-08-06 13:06:40 +00:00
AArch64FrameLowering.h [AArch64] NFC: Add generic StackOffset to describe scalable offsets. 2019-08-06 13:06:40 +00:00
AArch64GenRegisterBankInfo.def [AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms. 2019-07-03 01:49:06 +00:00
AArch64InstrAtomics.td
AArch64InstrFormats.td [AArch64][GlobalISel] Support the neg_addsub_shifted_imm32 pattern 2019-08-02 18:12:53 +00:00
AArch64InstrInfo.cpp [AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets. 2019-08-06 15:06:31 +00:00
AArch64InstrInfo.h [AArch64] NFC: Add generic StackOffset to describe scalable offsets. 2019-08-06 13:06:40 +00:00
AArch64InstrInfo.td [AArch64] Add support for Transactional Memory Extension (TME) 2019-07-31 12:52:17 +00:00
AArch64InstructionSelector.cpp [globalisel] Allow SrcOp to convert an APInt and render it as an immediate operand (MO.isImm() == true) 2019-08-06 17:16:27 +00:00
AArch64ISelDAGToDAG.cpp Basic codegen for MTE stack tagging. 2019-07-17 19:24:02 +00:00
AArch64ISelLowering.cpp [AArch64] Expand bcmp() for small block lengths 2019-08-05 18:09:14 +00:00
AArch64ISelLowering.h [Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold 2019-07-24 22:57:22 +00:00
AArch64LegalizerInfo.cpp [globalisel] Allow SrcOp to convert an APInt and render it as an immediate operand (MO.isImm() == true) 2019-08-06 17:16:27 +00:00
AArch64LegalizerInfo.h [GlobalISel] Translate calls to memcpy et al to G_INTRINSIC_W_SIDE_EFFECTs and legalize later. 2019-07-19 00:24:45 +00:00
AArch64LoadStoreOptimizer.cpp [AArch64] Remove scan-build "Value stored during its initialization is never read" warnings. NFCI. 2019-05-08 16:29:39 +00:00
AArch64MachineFunctionInfo.h Basic codegen for MTE stack tagging. 2019-07-17 19:24:02 +00:00
AArch64MacroFusion.cpp
AArch64MacroFusion.h
AArch64MCInstLower.cpp AArch64: Add a tagged-globals backend feature. 2019-07-31 20:14:19 +00:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PreLegalizerCombiner.cpp [GISel]: Add GISelKnownBits analysis 2019-08-06 17:18:29 +00:00
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp CodeGen: Introduce a class for registers 2019-06-24 15:50:29 +00:00
AArch64RegisterBankInfo.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
AArch64RegisterBankInfo.h [AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms. 2019-07-03 01:49:06 +00:00
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp [AArch64] NFC: Add generic StackOffset to describe scalable offsets. 2019-08-06 13:06:40 +00:00
AArch64RegisterInfo.h CodeGen: Introduce a class for registers 2019-06-24 15:50:29 +00:00
AArch64RegisterInfo.td
AArch64SchedA53.td [AArch64][SVE2] Add SVE2 target features to backend and TargetParser 2019-05-13 10:10:24 +00:00
AArch64SchedA57.td [AArch64][SVE2] Add SVE2 target features to backend and TargetParser 2019-05-13 10:10:24 +00:00
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td [AArch64][SVE2] Add SVE2 target features to backend and TargetParser 2019-05-13 10:10:24 +00:00
AArch64SchedExynosM1.td [AArch64][SVE2] Add SVE2 target features to backend and TargetParser 2019-05-13 10:10:24 +00:00
AArch64SchedExynosM3.td [AArch64][SVE2] Add SVE2 target features to backend and TargetParser 2019-05-13 10:10:24 +00:00
AArch64SchedExynosM4.td [AArch64][SVE2] Add SVE2 target features to backend and TargetParser 2019-05-13 10:10:24 +00:00
AArch64SchedFalkor.td [AArch64][SVE2] Add SVE2 target features to backend and TargetParser 2019-05-13 10:10:24 +00:00
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td [AArch64][SVE2] Add SVE2 target features to backend and TargetParser 2019-05-13 10:10:24 +00:00
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td [AArch64] Update for Exynos 2019-05-02 22:01:39 +00:00
AArch64SchedPredicates.td [AArch64] Update for Exynos 2019-05-02 22:01:39 +00:00
AArch64SchedThunderX2T99.td [AArch64][SVE2] Add SVE2 target features to backend and TargetParser 2019-05-13 10:10:24 +00:00
AArch64SchedThunderX.td [AArch64][SVE2] Add SVE2 target features to backend and TargetParser 2019-05-13 10:10:24 +00:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp Basic codegen for MTE stack tagging. 2019-07-17 19:24:02 +00:00
AArch64SelectionDAGInfo.h Basic codegen for MTE stack tagging. 2019-07-17 19:24:02 +00:00
AArch64SIMDInstrOpt.cpp
AArch64SpeculationHardening.cpp
AArch64StackOffset.h [AArch64] NFC: Add generic StackOffset to describe scalable offsets. 2019-08-06 13:06:40 +00:00
AArch64StackTagging.cpp Speculative fix for stack-tagging.ll failure. 2019-07-17 21:27:44 +00:00
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp [AArch64] Set preferred function alignment to 16 bytes on Neoverse N1 2019-08-05 17:38:58 +00:00
AArch64Subtarget.h AArch64: Add a tagged-globals backend feature. 2019-07-31 20:14:19 +00:00
AArch64SVEInstrInfo.td [AArch64][SVE2] Load/store instruction fixes 2019-07-31 09:10:36 +00:00
AArch64SystemOperands.td [AArch64] Define ETE and TRBE system registers 2019-07-26 09:19:08 +00:00
AArch64TargetMachine.cpp Basic MTE stack tagging instrumentation. 2019-07-17 19:24:12 +00:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp [AArch64] Expand bcmp() for small block lengths 2019-08-05 18:09:14 +00:00
AArch64TargetTransformInfo.h [AArch64] Expand bcmp() for small block lengths 2019-08-05 18:09:14 +00:00
CMakeLists.txt Basic MTE stack tagging instrumentation. 2019-07-17 19:24:12 +00:00
LLVMBuild.txt [AArch64] Add dependency from AArch64CodeGen to TransformUtils to fix -DBUILD_SHARED_LIBS=on link error after D64173/r366361 2019-07-18 01:53:08 +00:00
SVEInstrFormats.td [AArch64][SVE2] Load/store instruction fixes 2019-07-31 09:10:36 +00:00