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21 lines
743 B
TableGen
21 lines
743 B
TableGen
//=- AMDGPURegisterBank.td - Describe the AMDGPU Banks -------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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def SGPRRegBank : RegisterBank<"SGPR",
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[SReg_32, SReg_64, SReg_128, SReg_256, SReg_512]
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>;
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def VGPRRegBank : RegisterBank<"VGPR",
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[VGPR_32, VReg_64, VReg_96, VReg_128, VReg_256, VReg_512]
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>;
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def SCCRegBank : RegisterBank <"SCC", [SReg_32, SCC_CLASS]>;
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// It is helpful to distinguish conditions from ordinary SGPRs.
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def VCCRegBank : RegisterBank <"VCC", [SReg_64]>;
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