Elena Demikhovsky b3f8b2cb2e Optimized loading (zextload) of i1 value from memory. ... This patch is a partial revert of https://llvm.org/svn/llvm-project/llvm/trunk@237793. Extra "and" causes performance degradation. We assume that i1 is stored in zero-extended form. And store operation is responsible for zeroing upper bits. Differential Revision: http://reviews.llvm.org/D17541 llvm-svn: 261828		2016-02-25 07:05:12 +00:00
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AArch64	[CodeGenPrepare] Remove load-based heuristic	2016-02-25 00:23:27 +00:00
AMDGPU	AMDGPU: Add failing testcase for register coalescer	2016-02-22 23:45:42 +00:00
ARM	ARM: sink atomic release barrier as far as possible into cmpxchg.	2016-02-22 20:55:50 +00:00
BPF
CPP
Generic	Move test/CodeGen/Generic/pr26652.ll to test/CodeGen/X86/pr26652.ll and test it only on X86.	2016-02-25 00:12:18 +00:00
Hexagon
Inputs
Mips
MIR	When printing MIR, output to errs() rather than outs().	2016-02-19 00:18:46 +00:00
MSP430	MSP430InstrInfo::loadRegFromStackSlot forgets to set register def.	2016-02-24 15:15:02 +00:00
NVPTX	Don't tail-duplicate blocks that contain convergent instructions.	2016-02-22 17:50:52 +00:00
PowerPC	Fix for PR26690 take 2	2016-02-22 18:04:00 +00:00
SPARC
SystemZ	[SystemZ] Fix ABI for i128 argument and return types	2016-02-19 14:10:21 +00:00
Thumb
Thumb2
WebAssembly	Revert "[WebAssembly] Stackify code emitted by eliminateFrameIndex"	2016-02-23 22:13:21 +00:00
WinEH	[WinEH] Visit 'unwind to caller' catchswitches nested in catchswitches	2016-02-23 07:18:15 +00:00
X86	Optimized loading (zextload) of i1 value from memory.	2016-02-25 07:05:12 +00:00
XCore