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f80bcb1cba
Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
62 lines
1.4 KiB
LLVM
62 lines
1.4 KiB
LLVM
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s
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define i64 @dext(i64 %i) nounwind readnone {
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entry:
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; CHECK-LABEL: dext:
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; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
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%shr = lshr i64 %i, 5
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%and = and i64 %shr, 1023
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ret i64 %and
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}
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define i64 @dextm(i64 %i) nounwind readnone {
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entry:
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; CHECK-LABEL: dextm:
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; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
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%shr = lshr i64 %i, 5
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%and = and i64 %shr, 17179869183
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ret i64 %and
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}
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define i64 @dextu(i64 %i) nounwind readnone {
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entry:
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; CHECK-LABEL: dextu:
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; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
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%shr = lshr i64 %i, 34
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%and = and i64 %shr, 63
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ret i64 %and
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}
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define i64 @dins(i64 %i, i64 %j) nounwind readnone {
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entry:
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; CHECK-LABEL: dins:
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; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
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%shl2 = shl i64 %j, 8
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%and = and i64 %shl2, 261888
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%and3 = and i64 %i, -261889
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%or = or i64 %and3, %and
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ret i64 %or
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}
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define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
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entry:
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; CHECK-LABEL: dinsm:
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; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33
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%shl4 = shl i64 %j, 10
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%and = and i64 %shl4, 8796093021184
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%and5 = and i64 %i, -8796093021185
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%or = or i64 %and5, %and
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ret i64 %or
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}
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define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
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entry:
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; CHECK-LABEL: dinsu:
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; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
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%shl4 = shl i64 %j, 40
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%and = and i64 %shl4, 9006099743113216
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%and5 = and i64 %i, -9006099743113217
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%or = or i64 %and5, %and
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ret i64 %or
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}
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