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The instructions VLDM/VSTM can only access word-aligned memory locations and produce alignment fault if the condition is not met. The compiler currently generates VLDM/VSTM for v2f64 load/store regardless the alignment of the memory access. Instead, if a v2f64 load/store is not word-aligned, the compiler should generate VLD1/VST1. For each non double-word-aligned VLD1/VST1, a VREV instruction should be generated when targeting Big Endian. Differential Revision: https://reviews.llvm.org/D25281 llvm-svn: 283763
69 lines
2.3 KiB
LLVM
69 lines
2.3 KiB
LLVM
; RUN: llc -mtriple=armv7-eabi -mattr=+neon %s -o - | FileCheck %s --check-prefix=CHECK-LE
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; RUN: llc -mtriple=armv7eb-eabi -mattr=+neon %s -o - | FileCheck %s --check-prefix=CHECK-BE
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define void @ld_st_vec_i8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LE-LABEL: ld_st_vec_i8:
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;CHECK-LE: vld1.8 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
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;CHECK-LE-NOT: vrev
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;CHECK-LE: vst1.8 {[[D1]], [[D2]]}, [{{r[0-9]+}}]
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;CHECK-BE-LABEL: ld_st_vec_i8:
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;CHECK-BE: vld1.8 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
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;CHECK-BE: vrev64.8 [[Q1:q[0-9]+]], [[Q2:q[0-9]+]]
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;CHECK-BE: vrev64.8 [[Q1]], [[Q2]]
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;CHECK-BE: vst1.8 {[[D1]], [[D2]]}, [{{r[0-9]+}}]
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%load = load <16 x i8>, <16 x i8>* %A, align 1
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store <16 x i8> %load, <16 x i8>* %B, align 1
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ret void
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}
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define void @ld_st_vec_i16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LE-LABEL: ld_st_vec_i16:
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;CHECK-LE: vld1.16 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
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;CHECK-LE-NOT: vrev
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;CHECK-LE: vst1.16 {[[D1]], [[D2]]}, [{{r[0-9]+}}]
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;CHECK-BE-LABEL: ld_st_vec_i16:
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;CHECK-BE: vld1.16 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
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;CHECK-BE: vrev64.16 [[Q1:q[0-9]+]], [[Q2:q[0-9]+]]
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;CHECK-BE: vrev64.16 [[Q1]], [[Q2]]
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;CHECK-BE: vst1.16 {[[D1]], [[D2]]}, [{{r[0-9]+}}]
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%load = load <8 x i16>, <8 x i16>* %A, align 2
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store <8 x i16> %load, <8 x i16>* %B, align 2
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ret void
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}
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define void @ld_st_vec_i32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LE-LABEL: ld_st_vec_i32:
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;CHECK-LE: vld1.32 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
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;CHECK-LE-NOT: vrev
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;CHECK-LE: vst1.32 {[[D1]], [[D2]]}, [{{r[0-9]+}}]
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;CHECK-BE-LABEL: ld_st_vec_i32:
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;CHECK-BE: vldmia {{r[0-9]+}}, {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}
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;CHECK-BE-NOT: vrev
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;CHECK-BE: vstmia {{r[0-9]+}}, {[[D1]], [[D2]]}
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%load = load <4 x i32>, <4 x i32>* %A, align 4
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store <4 x i32> %load, <4 x i32>* %B, align 4
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ret void
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}
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define void @ld_st_vec_double(<2 x double>* %A, <2 x double>* %B) nounwind {
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;CHECK-LE-LABEL: ld_st_vec_double:
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;CHECK-LE: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
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;CHECK-LE-NOT: vrev
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;CHECK-LE: vst1.64 {[[D1]], [[D2]]}, [{{r[0-9]+}}]
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;CHECK-BE-LABEL: ld_st_vec_double:
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;CHECK-BE: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [{{r[0-9]+}}]
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;CHECK-BE-NOT: vrev
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;CHECK-BE: vst1.64 {[[D1]], [[D2]]}, [{{r[0-9]+}}]
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%load = load <2 x double>, <2 x double>* %A, align 8
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store <2 x double> %load, <2 x double>* %B, align 8
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ret void
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}
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