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32c979f9e1
r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. llvm-svn: 187492
66 lines
2.0 KiB
LLVM
66 lines
2.0 KiB
LLVM
; Test variable-sized allocas and addresses based on them in cases where
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; stack arguments are needed.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-D
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP
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declare i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 %f, i64 %g)
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; Allocate %length bytes and take addresses based on the result.
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; There are two stack arguments, so an offset of 160 + 2 * 8 == 176
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; is added to the copy of %r15.
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define i64 @f1(i64 %length, i64 %index) {
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; FIXME: a better sequence would be:
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;
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; lgr %r1, %r15
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; sgr %r1, %r2
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; nill %r1, 0xfff8
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; lgr %r15, %r1
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;
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; CHECK-LABEL: f1:
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; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2)
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; CHECK-DAG: nill [[REG1]], 65528
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; CHECK-DAG: lgr [[REG2:%r[0-5]]], %r15
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; CHECK: sgr [[REG2]], [[REG1]]
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; CHECK: lgr %r15, [[REG2]]
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;
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; CHECK-A-LABEL: f1:
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; CHECK-A: lgr %r15, %r1
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; CHECK-A: la %r2, 176(%r1)
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;
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; CHECK-B-LABEL: f1:
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; CHECK-B: lgr %r15, %r1
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; CHECK-B: la %r3, 177(%r1)
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;
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; CHECK-C-LABEL: f1:
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; CHECK-C: lgr %r15, %r1
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; CHECK-C: la %r4, 4095({{%r3,%r1|%r1,%r3}})
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;
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; CHECK-D-LABEL: f1:
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; CHECK-D: lgr %r15, %r1
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; CHECK-D: lay %r5, 4096({{%r3,%r1|%r1,%r3}})
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;
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; CHECK-E-LABEL: f1:
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; CHECK-E: lgr %r15, %r1
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; CHECK-E: lay %r6, 4271({{%r3,%r1|%r1,%r3}})
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;
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; CHECK-FP-LABEL: f1:
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; CHECK-FP: lgr %r11, %r15
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; CHECK-FP: lmg %r6, %r15, 224(%r11)
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%a = alloca i8, i64 %length
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%b = getelementptr i8 *%a, i64 1
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%cindex = add i64 %index, 3919
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%c = getelementptr i8 *%a, i64 %cindex
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%dindex = add i64 %index, 3920
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%d = getelementptr i8 *%a, i64 %dindex
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%eindex = add i64 %index, 4095
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%e = getelementptr i8 *%a, i64 %eindex
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%count = call i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 0, i64 0)
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%res = add i64 %count, 1
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ret i64 %res
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}
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