Nadav Rotem b537146d7f A DAGCombine optimization for mergeing consecutive stores to memory. The optimization ... is not profitable in many cases because modern processors perform multiple stores in parallel and merging stores prior to merging requires extra work. We handle two main cases: 1. Store of multiple consecutive constants: q->a = 3; q->4 = 5; In this case we store a single legal wide integer. 2. Store of multiple consecutive loads: int a = p->a; int b = p->b; q->a = a; q->b = b; In this case we load/store either ilegal vector registers or legal wide integer registers. llvm-svn: 165125		2012-10-03 16:11:15 +00:00
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ARM	Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to not propagate through implicit defs.	2012-10-03 08:29:36 +00:00
CellSPU	Fix broken tests.	2012-10-02 15:49:34 +00:00
CPP	test commit	2012-07-18 17:53:05 +00:00
Generic	BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle	2012-08-24 18:14:27 +00:00
Hexagon	LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the	2012-09-05 16:01:40 +00:00
MBlaze
Mips	checking test case for r164811. was an omission to not check this in. this was already approved	2012-10-01 21:35:06 +00:00
MSP430	Reapply r161633-161634 "Partition use lists so defs always come before uses.""	2012-08-10 00:21:30 +00:00
NVPTX
PowerPC	Specify MachinePointerInfo as refering to the argument value and offset of the	2012-09-24 20:47:19 +00:00
SPARC	Fix broken tests.	2012-10-02 15:49:34 +00:00
Thumb	Fix Thumb2 fixup kind in the integrated-as.	2012-09-01 15:06:36 +00:00
Thumb2	Add LLVM support for Swift.	2012-09-29 21:43:49 +00:00
X86	A DAGCombine optimization for mergeing consecutive stores to memory. The optimization	2012-10-03 16:11:15 +00:00
XCore