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b0a193db31
cannot be folded into target cmp instruction. - Avoid a phase ordering issue where early cmp optimization would prevent the later count-to-zero optimization. - Add missing checks which could cause LSR to reuse stride that does not have users. - Fix a bug in count-to-zero optimization code which failed to find the pre-inc iv's phi node. - Remove, tighten, loosen some incorrect checks disable valid transformations. - Quite a bit of code clean up. llvm-svn: 86969
38 lines
1.4 KiB
LLVM
38 lines
1.4 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic | FileCheck %s
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; rdar://7387640
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; FIXME: We still need to rewrite array reference iv of stride -4 with loop
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; count iv of stride -1.
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@G = external global i32 ; <i32*> [#uses=2]
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@array = external global i32* ; <i32**> [#uses=1]
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define arm_apcscc void @t() nounwind optsize {
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; CHECK: t:
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; CHECK: mov.w r2, #4000
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; CHECK: movw r3, #1001
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entry:
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%.pre = load i32* @G, align 4 ; <i32> [#uses=1]
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br label %bb
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bb: ; preds = %bb, %entry
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; CHECK: LBB1_1:
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; CHECK: subs r3, #1
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; CHECK: cmp r3, #0
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; CHECK: sub.w r2, r2, #4
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%0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1]
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%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
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%tmp5 = sub i32 1000, %indvar ; <i32> [#uses=1]
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%1 = load i32** @array, align 4 ; <i32*> [#uses=1]
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%scevgep = getelementptr i32* %1, i32 %tmp5 ; <i32*> [#uses=1]
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%2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
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%3 = add nsw i32 %2, %0 ; <i32> [#uses=2]
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store i32 %3, i32* @G, align 4
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%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
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%exitcond = icmp eq i32 %indvar.next, 1001 ; <i1> [#uses=1]
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br i1 %exitcond, label %return, label %bb
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return: ; preds = %bb
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ret void
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}
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