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b54a536d6f
This commit enables forming vector extloads for ARM.
It only does so for legal types, and when we can't fold the extension
in a wide/long form of the user instruction.
Enabling it for larger types isn't as good an idea on ARM as it is on
X86, because:
- we pretend that extloads are legal, but end up generating vld+vmov
- we have instructions like vld {dN, dM}, which can't be generated
when we "manually expand" extloads to vld+vmov.
For legal types, the combine doesn't fire that often: in the
integration tests only in a big endian testcase, where it removes a
pointless AND.
Related to rdar://19723053
Differential Revision: http://reviews.llvm.org/D7423
llvm-svn: 231396
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| .. | ||
| AArch64 | ||
| ARM | ||
| BPF | ||
| CPP | ||
| Generic | ||
| Hexagon | ||
| Inputs | ||
| Mips | ||
| MSP430 | ||
| NVPTX | ||
| PowerPC | ||
| R600 | ||
| SPARC | ||
| SystemZ | ||
| Thumb | ||
| Thumb2 | ||
| WinEH | ||
| X86 | ||
| XCore | ||