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b57cb76b6d
Almost all instructions that takes a 128 bits reg as input (fetch, export...) have the abilities to swizzle their argument and output. Instead of printing default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions print potentially optimized swizzles themselves. llvm-svn: 182124
43 lines
2.4 KiB
LLVM
43 lines
2.4 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 1
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;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 2
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;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 3
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;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 4
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;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 5
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;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 6
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;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 7
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;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 8
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;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 9
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;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 10
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;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 11
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;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 12
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;CHECK: TEX_SAMPLE_CT{{[0-9]+, T[0-9]+}}, 0, 0, 13
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;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 14
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;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 15
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;CHECK: TEX_SAMPLET{{[0-9]+, T[0-9]+}}, 0, 0, 16
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define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%addr = load <4 x float> addrspace(1)* %in
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%res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %addr, i32 0, i32 0, i32 1)
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%res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res1, i32 0, i32 0, i32 2)
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%res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res2, i32 0, i32 0, i32 3)
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%res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res3, i32 0, i32 0, i32 4)
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%res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res4, i32 0, i32 0, i32 5)
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%res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res5, i32 0, i32 0, i32 6)
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%res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res6, i32 0, i32 0, i32 7)
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%res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res7, i32 0, i32 0, i32 8)
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%res9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res8, i32 0, i32 0, i32 9)
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%res10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res9, i32 0, i32 0, i32 10)
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%res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res10, i32 0, i32 0, i32 11)
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%res12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res11, i32 0, i32 0, i32 12)
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%res13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res12, i32 0, i32 0, i32 13)
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%res14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res13, i32 0, i32 0, i32 14)
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%res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res14, i32 0, i32 0, i32 15)
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%res16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res15, i32 0, i32 0, i32 16)
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store <4 x float> %res16, <4 x float> addrspace(1)* %out
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ret void
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}
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declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
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