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dcd7a1bde2
Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 llvm-svn: 243638
33 lines
1.2 KiB
LLVM
33 lines
1.2 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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%struct.x = type { i32 }
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@i = common global i32 0, align 4
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define i32 @foobar(i32 signext %x) {
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entry:
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; CHECK-LABEL: foobar:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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%a = alloca %struct.x, align 4
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%c = alloca %struct.x*, align 4
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store i32 %x, i32* %x.addr, align 4
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%x1 = getelementptr inbounds %struct.x, %struct.x* %a, i32 0, i32 0
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%0 = load i32, i32* %x.addr, align 4
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store i32 %0, i32* %x1, align 4
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store %struct.x* %a, %struct.x** %c, align 4
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%1 = load %struct.x*, %struct.x** %c, align 4
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%x2 = getelementptr inbounds %struct.x, %struct.x* %1, i32 0, i32 0
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%2 = load i32, i32* %x2, align 4
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store i32 %2, i32* @i, align 4
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%3 = load i32, i32* %retval
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]])
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; CHECK-DAG: addiu $[[A_ADDR:[0-9]+]], $sp, 8
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; CHECK-DAG: sw $[[A_ADDR]], [[A_ADDR_FI:[0-9]+]]($sp)
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; CHECK-DAG: lw $[[A_ADDR2:[0-9]+]], [[A_ADDR_FI]]($sp)
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; CHECK-DAG: lw $[[A_X:[0-9]+]], 0($[[A_ADDR2]])
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; CHECK-DAG: sw $[[A_X]], 0($[[I_ADDR]])
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ret i32 %3
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}
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