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96 lines
3.9 KiB
LLVM
96 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; The first load produces address in a VGPR which is used in address calculation
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; of the second load (one inside the loop). The value is uniform and the inner
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; load correctly selected to use SADDR form, however the address is promoted to
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; vector registers because it all starts with a VGPR produced by the entry block
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; load.
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;
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; Check that we are changing SADDR form of a load to VADDR and do not have to use
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; readfirstlane instructions to move address from VGPRs into SGPRs.
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define amdgpu_kernel void @test_move_load_address_to_vgpr(i32 addrspace(1)* nocapture %arg) {
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; GCN-LABEL: test_move_load_address_to_vgpr:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_dword v1, v2, s[0:1] glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v3, s1
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; GCN-NEXT: v_add_u32_e32 v0, 0xffffff00, v1
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; GCN-NEXT: v_lshlrev_b64 v[1:2], 2, v[1:2]
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; GCN-NEXT: v_add_co_u32_e32 v1, vcc, s0, v1
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; GCN-NEXT: v_addc_co_u32_e32 v2, vcc, v3, v2, vcc
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; GCN-NEXT: BB0_1: ; %bb3
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: global_load_dword v3, v[1:2], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0
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; GCN-NEXT: v_add_co_u32_e64 v1, s[0:1], 4, v1
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; GCN-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
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; GCN-NEXT: s_and_b64 vcc, exec, vcc
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; GCN-NEXT: s_cbranch_vccz BB0_1
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; GCN-NEXT: ; %bb.2: ; %bb2
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; GCN-NEXT: s_endpgm
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bb:
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%i1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 0
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%i2 = load volatile i32, i32 addrspace(1)* %i1, align 4
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br label %bb3
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bb2: ; preds = %bb3
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ret void
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bb3: ; preds = %bb3, %bb
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%i = phi i32 [ %i2, %bb ], [ %i8, %bb3 ]
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%i4 = zext i32 %i to i64
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%i5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %i4
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%i6 = load volatile i32, i32 addrspace(1)* %i5, align 4
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%i8 = add nuw nsw i32 %i, 1
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%i9 = icmp eq i32 %i8, 256
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br i1 %i9, label %bb2, label %bb3
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}
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define amdgpu_kernel void @test_move_load_address_to_vgpr_d16_hi(i16 addrspace(1)* nocapture %arg) {
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; GCN-LABEL: test_move_load_address_to_vgpr_d16_hi:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_ushort v0, v1, s[0:1] glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: BB1_1: ; %bb3
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_lshlrev_b64 v[2:3], 1, v[0:1]
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; GCN-NEXT: v_mov_b32_e32 v0, s1
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; GCN-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2
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; GCN-NEXT: v_addc_co_u32_e32 v3, vcc, v0, v3, vcc
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; GCN-NEXT: global_load_short_d16_hi v0, v[2:3], off glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0x100, v0
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; GCN-NEXT: s_and_b64 vcc, exec, vcc
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; GCN-NEXT: s_cbranch_vccz BB1_1
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; GCN-NEXT: ; %bb.2: ; %bb2
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; GCN-NEXT: s_endpgm
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bb:
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%i1 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 0
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%load.pre = load volatile i16, i16 addrspace(1)* %i1, align 4
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%i2 = zext i16 %load.pre to i32
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br label %bb3
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bb2: ; preds = %bb3
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ret void
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bb3: ; preds = %bb3, %bb
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%i = phi i32 [ %i2, %bb ], [ %i8, %bb3 ]
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%i4 = zext i32 %i to i64
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%i5 = getelementptr inbounds i16, i16 addrspace(1)* %arg, i64 %i4
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%i6 = load volatile i16, i16 addrspace(1)* %i5, align 4
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%insertelt = insertelement <2 x i16> undef, i16 %i6, i32 1
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%i8 = bitcast <2 x i16> %insertelt to i32
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%i9 = icmp eq i32 %i8, 256
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br i1 %i9, label %bb2, label %bb3
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}
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