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92ee2a8454
Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 llvm-svn: 153766
8 lines
263 B
ArmAsm
8 lines
263 B
ArmAsm
@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
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vswp d1, d2
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vswp q1, q2
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@ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3]
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@ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]
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