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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
llvm-mirror/test/CodeGen
Chris Lattner b628208161 Finish implementing a readme entry: when inserting an i64 variable
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle.  This allows us to compile
vec_set-B.ll into:

_test3:
	movl	$1234567, %eax
	andl	4(%esp), %eax
	movd	%eax, %xmm0
	ret

instead of:

_test3:
	subl	$28, %esp
	movl	$1234567, %eax
	andl	32(%esp), %eax
	movl	%eax, (%esp)
	movl	$0, 4(%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48090
2008-03-09 05:42:06 +00:00
..
Alpha Remove llvm-upgrade and update tests. 2008-02-19 01:41:04 +00:00
ARM Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI. 2008-03-07 20:12:54 +00:00
CBackend add a testcase for misc vector stuff 2008-03-02 08:57:59 +00:00
CellSPU Refine Cell's i64 constant generation code to cover more constants where the 2008-03-06 04:02:54 +00:00
Generic some more spelling changes 2008-03-06 10:51:21 +00:00
IA64 Remove llvm-upgrade and update tests. 2008-02-19 01:41:04 +00:00
PowerPC upgrade this test 2008-03-09 00:32:10 +00:00
SPARC Remove llvm-upgrade and update tests. 2008-02-19 01:41:04 +00:00
X86 Finish implementing a readme entry: when inserting an i64 variable 2008-03-09 05:42:06 +00:00