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54 lines
1.8 KiB
LLVM
54 lines
1.8 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx -o %t -f
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; RUN: grep psrad %t | count 2
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; RUN: grep psraw %t | count 2
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; test vector shifts converted to proper SSE2 vector shifts when the shift
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; amounts are the same.
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; Note that x86 does have ashr
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define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
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entry:
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%ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
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store <2 x i64> %ashr, <2 x i64>* %dst
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ret void
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}
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define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
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entry:
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%ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
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store <4 x i32> %ashr, <4 x i32>* %dst
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ret void
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}
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define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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entry:
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%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
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%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
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%3 = insertelement <4 x i32> %2, i32 %amt, i32 3
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%ashr = ashr <4 x i32> %val, %3
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store <4 x i32> %ashr, <4 x i32>* %dst
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ret void
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}
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define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
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entry:
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%ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
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store <8 x i16> %ashr, <8 x i16>* %dst
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ret void
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}
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define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
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entry:
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%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
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%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
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%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
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%3 = insertelement <8 x i16> %0, i16 %amt, i32 3
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%4 = insertelement <8 x i16> %0, i16 %amt, i32 4
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%5 = insertelement <8 x i16> %0, i16 %amt, i32 5
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%6 = insertelement <8 x i16> %0, i16 %amt, i32 6
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%7 = insertelement <8 x i16> %0, i16 %amt, i32 7
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%ashr = ashr <8 x i16> %val, %7
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store <8 x i16> %ashr, <8 x i16>* %dst
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ret void
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} |