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46 lines
1.5 KiB
LLVM
46 lines
1.5 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare i1 @llvm.AMDGPU.class.f32(float, i32) #1
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declare i1 @llvm.AMDGPU.class.f64(double, i32) #1
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declare i32 @llvm.r600.read.tidig.x() #1
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declare float @llvm.fabs.f32(float) #1
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declare double @llvm.fabs.f64(double) #1
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; SI-LABEL: {{^}}test_isinf_pattern:
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; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x204{{$}}
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; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
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; SI-NOT: v_cmp
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; SI: s_endpgm
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define void @test_isinf_pattern(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%fabs = tail call float @llvm.fabs.f32(float %x) #1
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%cmp = fcmp oeq float %fabs, 0x7FF0000000000000
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%ext = zext i1 %cmp to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_not_isinf_pattern_0:
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; SI-NOT: v_cmp_class
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; SI: s_endpgm
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define void @test_not_isinf_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%fabs = tail call float @llvm.fabs.f32(float %x) #1
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%cmp = fcmp ueq float %fabs, 0x7FF0000000000000
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%ext = zext i1 %cmp to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_not_isinf_pattern_1:
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; SI-NOT: v_cmp_class
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; SI: s_endpgm
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define void @test_not_isinf_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
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%fabs = tail call float @llvm.fabs.f32(float %x) #1
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%cmp = fcmp oeq float %fabs, 0xFFF0000000000000
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%ext = zext i1 %cmp to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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