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277138a332
This is causing compilation timeouts on code with long sequences of local values and calls (i.e. foo(1); foo(2); foo(3); ...). It turns out that code coverage instrumentation is a great way to create sequences like this, which how our users ran into the issue in practice. Intel has a tool that detects these kinds of non-linear compile time issues, and Andy Kaylor reported it as PR37010. The current sinking code scans the whole basic block once per local value sink, which happens before emitting each call. In theory, local values should only be introduced to be used by instructions between the current flush point and the last flush point, so we should only need to scan those instructions. llvm-svn: 329822
38 lines
1.3 KiB
LLVM
38 lines
1.3 KiB
LLVM
; RUN: llc -fast-isel-sink-local-values -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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; Test load/store of global value from global offset table.
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@seed = common global i64 0, align 8
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define void @Initrand() nounwind {
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entry:
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; CHECK: @Initrand
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; CHECK: adrp [[REG:x[0-9]+]], _seed@GOTPAGE
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; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG]], _seed@GOTPAGEOFF{{\]}}
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; CHECK: str {{x[0-9]+}}, {{\[}}[[REG2]]{{\]}}
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store i64 74755, i64* @seed, align 8
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ret void
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}
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define i32 @Rand() nounwind {
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entry:
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; CHECK: @Rand
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; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE
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; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}}
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; CHECK: ldr [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}}
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; CHECK: mov [[REG4:x[0-9]+]], #1309
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; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]]
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; CHECK: mov [[REG3:x[0-9]+]], #13849
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; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]]
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; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff
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; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}}
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; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}}
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%0 = load i64, i64* @seed, align 8
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%mul = mul nsw i64 %0, 1309
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%add = add nsw i64 %mul, 13849
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%and = and i64 %add, 65535
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store i64 %and, i64* @seed, align 8
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%1 = load i64, i64* @seed, align 8
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%conv = trunc i64 %1 to i32
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ret i32 %conv
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}
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