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ee6b7b1495
This commit makes it so that if you outline a def of some register, then the call instruction created by the outliner actually reflects that the register is defined by the call. It also makes it so that outlined functions don't have the TracksLiveness property. Outlined calls shouldn't break liveness assumptions that someone might make. This also un-XFAILs the noredzone test, and updates the calls test. llvm-svn: 331095
78 lines
2.5 KiB
LLVM
78 lines
2.5 KiB
LLVM
; RUN: llc -verify-machineinstrs -enable-machine-outliner %s -o - | FileCheck %s
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; RUN: llc -verify-machineinstrs -enable-machine-outliner -aarch64-redzone %s -o - | FileCheck %s -check-prefix=REDZONE
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; Ensure that the MachineOutliner does not fire on functions which use a
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; redzone. We don't care about what's actually outlined here. We just want to
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; force behaviour in the outliner to make sure that it never acts on anything
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; that might have a redzone.
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target triple = "arm64----"
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@x = common global i32 0, align 4
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declare void @baz() #0
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; In AArch64FrameLowering, there are a couple special early exit cases where we
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; *know* we don't use a redzone. The GHC calling convention is one of these
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; cases. Make sure that we know we don't have a redzone even in these cases.
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define cc 10 void @bar() #0 {
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; CHECK-LABEL: bar
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; CHECK: bl OUTLINED_FUNCTION
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; REDZONE-LABEL: bar
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; REDZONE: bl OUTLINED_FUNCTION
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%1 = load i32, i32* @x, align 4
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%2 = add nsw i32 %1, 1
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store i32 %2, i32* @x, align 4
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call void @baz()
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%3 = load i32, i32* @x, align 4
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%4 = add nsw i32 %3, 1
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store i32 %4, i32* @x, align 4
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call void @baz()
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%5 = load i32, i32* @x, align 4
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%6 = add nsw i32 %5, 1
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store i32 %6, i32* @x, align 4
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ret void
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}
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; foo() should have a redzone when compiled with -aarch64-redzone, and no
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; redzone otherwise.
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define void @foo() #0 {
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; CHECK-LABEL: foo
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; CHECK: bl OUTLINED_FUNCTION
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; REDZONE-LABEL: foo
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; REDZONE-NOT: bl OUTLINED_FUNCTION
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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store i32 0, i32* %1, align 4
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store i32 0, i32* %2, align 4
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store i32 0, i32* %3, align 4
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store i32 0, i32* %4, align 4
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%5 = load i32, i32* %1, align 4
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%6 = add nsw i32 %5, 1
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store i32 %6, i32* %1, align 4
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%7 = load i32, i32* %3, align 4
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%8 = add nsw i32 %7, 1
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store i32 %8, i32* %3, align 4
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%9 = load i32, i32* %4, align 4
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%10 = add nsw i32 %9, 1
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store i32 %10, i32* %4, align 4
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%11 = load i32, i32* %2, align 4
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%12 = add nsw i32 %11, 1
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store i32 %12, i32* %2, align 4
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%13 = load i32, i32* %1, align 4
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%14 = add nsw i32 %13, 1
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store i32 %14, i32* %1, align 4
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%15 = load i32, i32* %3, align 4
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%16 = add nsw i32 %15, 1
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store i32 %16, i32* %3, align 4
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%17 = load i32, i32* %4, align 4
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%18 = add nsw i32 %17, 1
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store i32 %18, i32* %4, align 4
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%19 = load i32, i32* %2, align 4
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%20 = add nsw i32 %19, -1
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store i32 %20, i32* %2, align 4
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ret void
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}
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attributes #0 = { noinline nounwind optnone }
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