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ba0a393451
This adds support for the MCU psABI in a way different from r251223 and r251224, basically reverting most of these two patches. The problem with the approach taken in r251223/4 is that it only handled libcalls that originated from the backend. However, the mid-end also inserts quite a few libcalls and assumes these use the platform's default calling convention. The previous patch tried to insert inregs when necessary both in the FE and, somewhat hackily, in the CG. Instead, we now define a new default calling convention for the MCU, which doesn't use inreg marking at all, similarly to what x86-64 does. Differential Revision: http://reviews.llvm.org/D15054 llvm-svn: 256494
203 lines
7.2 KiB
C++
203 lines
7.2 KiB
C++
//===-- llvm/Target/TargetCallingConv.h - Calling Convention ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines types for working with calling-convention information.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETCALLINGCONV_H
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#define LLVM_TARGET_TARGETCALLINGCONV_H
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/MathExtras.h"
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#include <string>
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#include <limits.h>
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namespace llvm {
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namespace ISD {
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struct ArgFlagsTy {
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private:
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static const uint64_t NoFlagSet = 0ULL;
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static const uint64_t ZExt = 1ULL<<0; ///< Zero extended
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static const uint64_t ZExtOffs = 0;
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static const uint64_t SExt = 1ULL<<1; ///< Sign extended
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static const uint64_t SExtOffs = 1;
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static const uint64_t InReg = 1ULL<<2; ///< Passed in register
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static const uint64_t InRegOffs = 2;
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static const uint64_t SRet = 1ULL<<3; ///< Hidden struct-ret ptr
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static const uint64_t SRetOffs = 3;
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static const uint64_t ByVal = 1ULL<<4; ///< Struct passed by value
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static const uint64_t ByValOffs = 4;
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static const uint64_t Nest = 1ULL<<5; ///< Nested fn static chain
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static const uint64_t NestOffs = 5;
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static const uint64_t Returned = 1ULL<<6; ///< Always returned
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static const uint64_t ReturnedOffs = 6;
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static const uint64_t ByValAlign = 0xFULL<<7; ///< Struct alignment
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static const uint64_t ByValAlignOffs = 7;
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static const uint64_t Split = 1ULL<<11;
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static const uint64_t SplitOffs = 11;
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static const uint64_t InAlloca = 1ULL<<12; ///< Passed with inalloca
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static const uint64_t InAllocaOffs = 12;
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static const uint64_t SplitEnd = 1ULL<<13; ///< Last part of a split
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static const uint64_t SplitEndOffs = 13;
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static const uint64_t OrigAlign = 0x1FULL<<27;
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static const uint64_t OrigAlignOffs = 27;
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static const uint64_t ByValSize = 0x3fffffffULL<<32; ///< Struct size
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static const uint64_t ByValSizeOffs = 32;
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static const uint64_t InConsecutiveRegsLast = 0x1ULL<<62; ///< Struct size
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static const uint64_t InConsecutiveRegsLastOffs = 62;
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static const uint64_t InConsecutiveRegs = 0x1ULL<<63; ///< Struct size
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static const uint64_t InConsecutiveRegsOffs = 63;
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static const uint64_t One = 1ULL; ///< 1 of this type, for shifts
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uint64_t Flags;
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public:
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ArgFlagsTy() : Flags(0) { }
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bool isZExt() const { return Flags & ZExt; }
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void setZExt() { Flags |= One << ZExtOffs; }
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bool isSExt() const { return Flags & SExt; }
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void setSExt() { Flags |= One << SExtOffs; }
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bool isInReg() const { return Flags & InReg; }
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void setInReg() { Flags |= One << InRegOffs; }
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bool isSRet() const { return Flags & SRet; }
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void setSRet() { Flags |= One << SRetOffs; }
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bool isByVal() const { return Flags & ByVal; }
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void setByVal() { Flags |= One << ByValOffs; }
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bool isInAlloca() const { return Flags & InAlloca; }
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void setInAlloca() { Flags |= One << InAllocaOffs; }
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bool isNest() const { return Flags & Nest; }
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void setNest() { Flags |= One << NestOffs; }
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bool isReturned() const { return Flags & Returned; }
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void setReturned() { Flags |= One << ReturnedOffs; }
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bool isInConsecutiveRegs() const { return Flags & InConsecutiveRegs; }
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void setInConsecutiveRegs() { Flags |= One << InConsecutiveRegsOffs; }
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bool isInConsecutiveRegsLast() const { return Flags & InConsecutiveRegsLast; }
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void setInConsecutiveRegsLast() { Flags |= One << InConsecutiveRegsLastOffs; }
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unsigned getByValAlign() const {
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return (unsigned)
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((One << ((Flags & ByValAlign) >> ByValAlignOffs)) / 2);
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}
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void setByValAlign(unsigned A) {
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Flags = (Flags & ~ByValAlign) |
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(uint64_t(Log2_32(A) + 1) << ByValAlignOffs);
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}
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bool isSplit() const { return Flags & Split; }
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void setSplit() { Flags |= One << SplitOffs; }
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bool isSplitEnd() const { return Flags & SplitEnd; }
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void setSplitEnd() { Flags |= One << SplitEndOffs; }
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unsigned getOrigAlign() const {
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return (unsigned)
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((One << ((Flags & OrigAlign) >> OrigAlignOffs)) / 2);
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}
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void setOrigAlign(unsigned A) {
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Flags = (Flags & ~OrigAlign) |
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(uint64_t(Log2_32(A) + 1) << OrigAlignOffs);
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}
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unsigned getByValSize() const {
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return (unsigned)((Flags & ByValSize) >> ByValSizeOffs);
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}
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void setByValSize(unsigned S) {
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Flags = (Flags & ~ByValSize) | (uint64_t(S) << ByValSizeOffs);
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}
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/// getRawBits - Represent the flags as a bunch of bits.
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uint64_t getRawBits() const { return Flags; }
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};
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/// InputArg - This struct carries flags and type information about a
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/// single incoming (formal) argument or incoming (from the perspective
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/// of the caller) return value virtual register.
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///
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struct InputArg {
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ArgFlagsTy Flags;
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MVT VT;
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EVT ArgVT;
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bool Used;
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/// Index original Function's argument.
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unsigned OrigArgIndex;
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/// Sentinel value for implicit machine-level input arguments.
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static const unsigned NoArgIndex = UINT_MAX;
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/// Offset in bytes of current input value relative to the beginning of
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/// original argument. E.g. if argument was splitted into four 32 bit
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/// registers, we got 4 InputArgs with PartOffsets 0, 4, 8 and 12.
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unsigned PartOffset;
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InputArg() : VT(MVT::Other), Used(false) {}
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InputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
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unsigned origIdx, unsigned partOffs)
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: Flags(flags), Used(used), OrigArgIndex(origIdx), PartOffset(partOffs) {
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VT = vt.getSimpleVT();
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ArgVT = argvt;
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}
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bool isOrigArg() const {
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return OrigArgIndex != NoArgIndex;
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}
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unsigned getOrigArgIndex() const {
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assert(OrigArgIndex != NoArgIndex && "Implicit machine-level argument");
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return OrigArgIndex;
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}
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};
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/// OutputArg - This struct carries flags and a value for a
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/// single outgoing (actual) argument or outgoing (from the perspective
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/// of the caller) return value virtual register.
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///
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struct OutputArg {
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ArgFlagsTy Flags;
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MVT VT;
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EVT ArgVT;
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/// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
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bool IsFixed;
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/// Index original Function's argument.
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unsigned OrigArgIndex;
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/// Offset in bytes of current output value relative to the beginning of
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/// original argument. E.g. if argument was splitted into four 32 bit
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/// registers, we got 4 OutputArgs with PartOffsets 0, 4, 8 and 12.
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unsigned PartOffset;
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OutputArg() : IsFixed(false) {}
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OutputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool isfixed,
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unsigned origIdx, unsigned partOffs)
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: Flags(flags), IsFixed(isfixed), OrigArgIndex(origIdx),
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PartOffset(partOffs) {
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VT = vt.getSimpleVT();
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ArgVT = argvt;
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}
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};
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}
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} // end llvm namespace
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#endif
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