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b5fde80c0e
For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769
56 lines
2.0 KiB
TableGen
56 lines
2.0 KiB
TableGen
//===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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include "RISCVInstrFormats.td"
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def simm12 : Operand<i32>;
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// As noted in RISCVRegisterInfo.td, the hope is that support for
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// variable-sized register classes will mean that instruction definitions do
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// not need to be duplicated for 32-bit and 64-bit register classes. For now
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// we use 'GPR', which is 32-bit. When codegen for both RV32 and RV64 is
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// added, we will need to duplicate instruction definitions unless a proposal
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// like <http://lists.llvm.org/pipermail/llvm-dev/2016-September/105027.html>
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// is adopted.
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class ALU_ri<bits<3> funct3, string OpcodeStr> :
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FI<funct3, 0b0010011, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
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OpcodeStr#"\t$rd, $rs1, $imm12", []>
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{
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}
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def ADDI : ALU_ri<0b000, "addi">;
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def SLTI : ALU_ri<0b010, "slti">;
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def SLTIU : ALU_ri<0b011, "sltiu">;
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def XORI : ALU_ri<0b100, "xori">;
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def ORI : ALU_ri<0b110, "ori">;
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def ANDI : ALU_ri<0b111, "andi">;
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class ALU_rr<bits<7> funct7, bits<3> funct3, string OpcodeStr> :
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FR<funct7, funct3, 0b0110011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
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OpcodeStr#"\t$rd, $rs1, $rs2", []>
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{
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}
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def ADD : ALU_rr<0b0000000, 0b000, "add">;
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def SUB : ALU_rr<0b0100000, 0b000, "sub">;
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def SLL : ALU_rr<0b0000000, 0b001, "sll">;
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def SLT : ALU_rr<0b0000000, 0b010, "slt">;
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def SLTU : ALU_rr<0b0000000, 0b011, "sltu">;
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def XOR : ALU_rr<0b0000000, 0b100, "xor">;
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def SRL : ALU_rr<0b0000000, 0b101, "srl">;
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def SRA : ALU_rr<0b0100000, 0b101, "sra">;
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def OR : ALU_rr<0b0000000, 0b110, "or">;
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def AND : ALU_rr<0b0000000, 0b111, "and">;
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