Nicolai Haehnle b70d32840d AMDGPU: Move v_readlane lane select from VGPR to SGPR ... Summary: Fix a compiler bug when the lane select happens to end up in a VGPR. Clarify the semantic of the corresponding intrinsic to be that of the corresponding GLSL: the lane select must be uniform across a wave front, otherwise results are undefined. Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D32343 llvm-svn: 301197		2017-04-24 17:17:36 +00:00
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AArch64	Fix testcase: s/CHECKNEXT/CHECK-NEXT/	2017-04-22 23:43:44 +00:00
AMDGPU	AMDGPU: Move v_readlane lane select from VGPR to SGPR	2017-04-24 17:17:36 +00:00
ARM	[ARM] GlobalISel: Legalize s8 and s16 G_(S|U)DIV	2017-04-24 09:12:19 +00:00
AVR	[AVR] Remove the 'multibyte' asm test	2017-04-19 12:13:45 +00:00
BPF	[bpf] Fix memory offset check for loads and stores	2017-04-13 22:24:13 +00:00
Generic	[Hexagon] Unxfail passing tests	2017-04-13 16:05:35 +00:00
Hexagon	[Hexagon] Generate proper offset in opt-addr-mode	2017-04-19 15:15:51 +00:00
Inputs
Lanai
Mips	[mips][msa] Mask vectors holding shift amounts	2017-04-20 13:26:46 +00:00
MIR
MSP430
NVPTX
PowerPC	[DAG] add splat vector support for 'xor' in SimplifyDemandedBits	2017-04-19 21:23:09 +00:00
SPARC
SystemZ	[SystemZ] Update kill-flag in splitMove().	2017-04-24 12:40:28 +00:00
Thumb	[ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs	2017-04-23 06:58:08 +00:00
Thumb2
WebAssembly	[WebAssembly] Fix WebAssemblyOptimizeReturned after r300367	2017-04-17 21:40:28 +00:00
WinEH
X86	[GlobalISel][X86] Lower FormalArgument/Ret using G_MERGE_VALUES/G_UNMERGE_VALUES.	2017-04-24 17:05:52 +00:00
XCore