mirror of
https://github.com/RPCS3/llvm-mirror.git
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a686678676
The Printer will now print instructions with the correct alignment specifier syntax, like
vld1.8 {d16}, [r0:64]
llvm-svn: 175884
129 lines
4.8 KiB
LLVM
129 lines
4.8 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon -fast-isel=0 -O0 | FileCheck %s
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define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vst3i8:
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;Check the alignment value. Max for this instruction is 64 bits:
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;This test runs at -O0 so do not check for specific register numbers.
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;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32)
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ret void
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}
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define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vst3i16:
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;CHECK: vst3.16
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst3.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
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ret void
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}
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define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vst3i32:
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;CHECK: vst3.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
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ret void
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}
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;Check for a post-increment updating store.
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define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind {
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;CHECK: vst3i32_update:
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;CHECK: vst3.32 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
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%A = load i32** %ptr
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
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%tmp2 = getelementptr i32* %A, i32 6
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store i32* %tmp2, i32** %ptr
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ret void
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}
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define void @vst3f(float* %A, <2 x float>* %B) nounwind {
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;CHECK: vst3f:
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;CHECK: vst3.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vst3.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
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ret void
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}
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define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
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;CHECK: vst3i64:
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;Check the alignment value. Max for this instruction is 64 bits:
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;This test runs at -O0 so do not check for specific register numbers.
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;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = load <1 x i64>* %B
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call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16)
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ret void
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}
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define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
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;CHECK: vst3Qi8:
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;Check the alignment value. Max for this instruction is 64 bits:
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;This test runs at -O0 so do not check for specific register numbers.
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;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]!
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;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
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%tmp1 = load <16 x i8>* %B
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call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32)
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ret void
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}
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define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK: vst3Qi16:
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;CHECK: vst3.16
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;CHECK: vst3.16
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>* %B
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call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
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ret void
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}
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;Check for a post-increment updating store.
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define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind {
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;CHECK: vst3Qi16_update:
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;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
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;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
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%A = load i16** %ptr
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>* %B
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call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
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%tmp2 = getelementptr i16* %A, i32 24
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store i16* %tmp2, i16** %ptr
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ret void
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}
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define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK: vst3Qi32:
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;CHECK: vst3.32
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;CHECK: vst3.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <4 x i32>* %B
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call void @llvm.arm.neon.vst3.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1)
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ret void
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}
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define void @vst3Qf(float* %A, <4 x float>* %B) nounwind {
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;CHECK: vst3Qf:
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;CHECK: vst3.32
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;CHECK: vst3.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <4 x float>* %B
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call void @llvm.arm.neon.vst3.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
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ret void
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}
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declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst3.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst3.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst3.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
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declare void @llvm.arm.neon.vst3.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, i32) nounwind
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declare void @llvm.arm.neon.vst3.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst3.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst3.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst3.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
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