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1431b3c2f5
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. llvm-svn: 181204
323 lines
11 KiB
LLVM
323 lines
11 KiB
LLVM
; Test the handling of base + displacement addresses for large frames,
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; in cases where both 12-bit and 20-bit displacements are allowed.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s
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; This file tests what happens when a displacement is converted from
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; being relative to the start of a frame object to being relative to
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; the frame itself. In some cases the test is only possible if two
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; objects are allocated.
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;
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; Rather than rely on a particular order for those objects, the tests
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; instead allocate two objects of the same size and apply the test to
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; both of them. For consistency, all tests follow this model, even if
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; one object would actually be enough.
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; First check the highest offset that is in range of the 12-bit form.
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;
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; The last in-range doubleword offset is 4088. Since the frame has an
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; emergency spill slot at 160(%r15), the amount that we need to allocate
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; in order to put another object at offset 4088 is 4088 - 168 = 3920 bytes.
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define void @f1() {
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; CHECK-NOFP: f1:
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; CHECK-NOFP: mvi 4095(%r15), 42
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f1:
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; CHECK-FP: mvi 4095(%r11), 42
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; CHECK-FP: br %r14
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%region1 = alloca [3920 x i8], align 8
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%region2 = alloca [3920 x i8], align 8
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%ptr1 = getelementptr inbounds [3920 x i8]* %region1, i64 0, i64 7
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%ptr2 = getelementptr inbounds [3920 x i8]* %region2, i64 0, i64 7
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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ret void
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}
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; Test the first offset that is out-of-range of the 12-bit form.
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define void @f2() {
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; CHECK-NOFP: f2:
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; CHECK-NOFP: mviy 4096(%r15), 42
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f2:
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; CHECK-FP: mviy 4096(%r11), 42
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; CHECK-FP: br %r14
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%region1 = alloca [3920 x i8], align 8
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%region2 = alloca [3920 x i8], align 8
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%ptr1 = getelementptr inbounds [3920 x i8]* %region1, i64 0, i64 8
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%ptr2 = getelementptr inbounds [3920 x i8]* %region2, i64 0, i64 8
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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ret void
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}
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; Test the last offset that is in range of the 20-bit form.
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;
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; The last in-range doubleword offset is 524280, so by the same reasoning
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; as above, we need to allocate objects of 524280 - 168 = 524122 bytes.
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define void @f3() {
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; CHECK-NOFP: f3:
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; CHECK-NOFP: mviy 524287(%r15), 42
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f3:
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; CHECK-FP: mviy 524287(%r11), 42
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; CHECK-FP: br %r14
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%region1 = alloca [524112 x i8], align 8
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%region2 = alloca [524112 x i8], align 8
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%ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 7
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%ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 7
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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ret void
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}
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; Test the first out-of-range offset. We can't use an index register here,
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; and the offset is also out of LAY's range, so expect a constant load
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; followed by an addition.
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define void @f4() {
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; CHECK-NOFP: f4:
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; CHECK-NOFP: llilh %r1, 8
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; CHECK-NOFP: agr %r1, %r15
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; CHECK-NOFP: mvi 0(%r1), 42
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f4:
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; CHECK-FP: llilh %r1, 8
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; CHECK-FP: agr %r1, %r11
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; CHECK-FP: mvi 0(%r1), 42
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; CHECK-FP: br %r14
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%region1 = alloca [524112 x i8], align 8
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%region2 = alloca [524112 x i8], align 8
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%ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8
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%ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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ret void
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}
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; Add 4095 to the previous offset, to test the other end of the MVI range.
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; The instruction will actually be STCY before frame lowering.
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define void @f5() {
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; CHECK-NOFP: f5:
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; CHECK-NOFP: llilh %r1, 8
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; CHECK-NOFP: agr %r1, %r15
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; CHECK-NOFP: mvi 4095(%r1), 42
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f5:
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; CHECK-FP: llilh %r1, 8
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; CHECK-FP: agr %r1, %r11
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; CHECK-FP: mvi 4095(%r1), 42
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; CHECK-FP: br %r14
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%region1 = alloca [524112 x i8], align 8
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%region2 = alloca [524112 x i8], align 8
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%ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 4103
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%ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 4103
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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ret void
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}
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; Test the next offset after that, which uses MVIY instead of MVI.
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define void @f6() {
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; CHECK-NOFP: f6:
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; CHECK-NOFP: llilh %r1, 8
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; CHECK-NOFP: agr %r1, %r15
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; CHECK-NOFP: mviy 4096(%r1), 42
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f6:
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; CHECK-FP: llilh %r1, 8
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; CHECK-FP: agr %r1, %r11
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; CHECK-FP: mviy 4096(%r1), 42
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; CHECK-FP: br %r14
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%region1 = alloca [524112 x i8], align 8
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%region2 = alloca [524112 x i8], align 8
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%ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 4104
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%ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 4104
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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ret void
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}
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; Now try an offset of 524287 from the start of the object, with the
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; object being at offset 1048576 (1 << 20). The backend prefers to create
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; anchors 0x10000 bytes apart, so that the high part can be loaded using
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; LLILH while still using MVI in more cases than 0x40000 anchors would.
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define void @f7() {
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; CHECK-NOFP: f7:
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; CHECK-NOFP: llilh %r1, 23
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; CHECK-NOFP: agr %r1, %r15
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; CHECK-NOFP: mviy 65535(%r1), 42
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f7:
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; CHECK-FP: llilh %r1, 23
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; CHECK-FP: agr %r1, %r11
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; CHECK-FP: mviy 65535(%r1), 42
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; CHECK-FP: br %r14
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%region1 = alloca [1048408 x i8], align 8
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%region2 = alloca [1048408 x i8], align 8
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%ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287
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%ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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ret void
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}
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; Keep the object-relative offset the same but bump the size of the
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; objects by one doubleword.
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define void @f8() {
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; CHECK-NOFP: f8:
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; CHECK-NOFP: llilh %r1, 24
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; CHECK-NOFP: agr %r1, %r15
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; CHECK-NOFP: mvi 7(%r1), 42
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f8:
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; CHECK-FP: llilh %r1, 24
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; CHECK-FP: agr %r1, %r11
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; CHECK-FP: mvi 7(%r1), 42
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; CHECK-FP: br %r14
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%region1 = alloca [1048416 x i8], align 8
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%region2 = alloca [1048416 x i8], align 8
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%ptr1 = getelementptr inbounds [1048416 x i8]* %region1, i64 0, i64 524287
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%ptr2 = getelementptr inbounds [1048416 x i8]* %region2, i64 0, i64 524287
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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ret void
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}
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; Check a case where the original displacement is out of range. The backend
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; should force separate address logic from the outset. We don't yet do any
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; kind of anchor optimization, so there should be no offset on the MVI itself.
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;
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; Before frame lowering this is an LA followed by the AGFI seen below.
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; The LA then gets lowered into the LLILH/LA form. The exact sequence
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; isn't that important though.
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define void @f9() {
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; CHECK-NOFP: f9:
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; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16
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; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)
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; CHECK-NOFP: agfi [[R2]], 524288
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; CHECK-NOFP: mvi 0([[R2]]), 42
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f9:
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; CHECK-FP: llilh [[R1:%r[1-5]]], 16
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; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
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; CHECK-FP: agfi [[R2]], 524288
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; CHECK-FP: mvi 0([[R2]]), 42
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; CHECK-FP: br %r14
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%region1 = alloca [1048416 x i8], align 8
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%region2 = alloca [1048416 x i8], align 8
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%ptr1 = getelementptr inbounds [1048416 x i8]* %region1, i64 0, i64 524288
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%ptr2 = getelementptr inbounds [1048416 x i8]* %region2, i64 0, i64 524288
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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ret void
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}
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; Repeat f4 in a case that needs the emergency spill slot (because all
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; call-clobbered registers are live and no call-saved ones have been
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; allocated).
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define void @f10(i32 *%vptr) {
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; CHECK-NOFP: f10:
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; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15)
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; CHECK-NOFP: llilh [[REGISTER]], 8
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; CHECK-NOFP: agr [[REGISTER]], %r15
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; CHECK-NOFP: mvi 0([[REGISTER]]), 42
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; CHECK-NOFP: lg [[REGISTER]], 160(%r15)
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f10:
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; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11)
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; CHECK-FP: llilh [[REGISTER]], 8
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; CHECK-FP: agr [[REGISTER]], %r11
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; CHECK-FP: mvi 0([[REGISTER]]), 42
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; CHECK-FP: lg [[REGISTER]], 160(%r11)
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; CHECK-FP: br %r14
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%i0 = load volatile i32 *%vptr
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%i1 = load volatile i32 *%vptr
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%i3 = load volatile i32 *%vptr
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%i4 = load volatile i32 *%vptr
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%i5 = load volatile i32 *%vptr
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%region1 = alloca [524112 x i8], align 8
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%region2 = alloca [524112 x i8], align 8
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%ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8
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%ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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store volatile i32 %i0, i32 *%vptr
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store volatile i32 %i1, i32 *%vptr
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store volatile i32 %i3, i32 *%vptr
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store volatile i32 %i4, i32 *%vptr
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store volatile i32 %i5, i32 *%vptr
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ret void
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}
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; And again with maximum register pressure. The only spill slot that the
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; NOFP case needs is the emergency one, so the offsets are the same as for f4.
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; However, the FP case uses %r11 as the frame pointer and must therefore
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; spill a second register. This leads to an extra displacement of 8.
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define void @f11(i32 *%vptr) {
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; CHECK-NOFP: f11:
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; CHECK-NOFP: stmg %r6, %r15,
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; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15)
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; CHECK-NOFP: llilh [[REGISTER]], 8
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; CHECK-NOFP: agr [[REGISTER]], %r15
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; CHECK-NOFP: mvi 0([[REGISTER]]), 42
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; CHECK-NOFP: lg [[REGISTER]], 160(%r15)
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; CHECK-NOFP: lmg %r6, %r15,
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; CHECK-NOFP: br %r14
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;
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; CHECK-FP: f11:
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; CHECK-FP: stmg %r6, %r15,
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; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11)
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; CHECK-FP: llilh [[REGISTER]], 8
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; CHECK-FP: agr [[REGISTER]], %r11
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; CHECK-FP: mvi 8([[REGISTER]]), 42
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; CHECK-FP: lg [[REGISTER]], 160(%r11)
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; CHECK-FP: lmg %r6, %r15,
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; CHECK-FP: br %r14
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%i0 = load volatile i32 *%vptr
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%i1 = load volatile i32 *%vptr
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%i3 = load volatile i32 *%vptr
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%i4 = load volatile i32 *%vptr
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%i5 = load volatile i32 *%vptr
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%i6 = load volatile i32 *%vptr
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%i7 = load volatile i32 *%vptr
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%i8 = load volatile i32 *%vptr
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%i9 = load volatile i32 *%vptr
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%i10 = load volatile i32 *%vptr
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%i11 = load volatile i32 *%vptr
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%i12 = load volatile i32 *%vptr
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%i13 = load volatile i32 *%vptr
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%i14 = load volatile i32 *%vptr
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%region1 = alloca [524112 x i8], align 8
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%region2 = alloca [524112 x i8], align 8
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%ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8
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%ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8
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store volatile i8 42, i8 *%ptr1
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store volatile i8 42, i8 *%ptr2
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store volatile i32 %i0, i32 *%vptr
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store volatile i32 %i1, i32 *%vptr
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store volatile i32 %i3, i32 *%vptr
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store volatile i32 %i4, i32 *%vptr
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store volatile i32 %i5, i32 *%vptr
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store volatile i32 %i6, i32 *%vptr
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store volatile i32 %i7, i32 *%vptr
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store volatile i32 %i8, i32 *%vptr
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store volatile i32 %i9, i32 *%vptr
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store volatile i32 %i10, i32 *%vptr
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store volatile i32 %i11, i32 *%vptr
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store volatile i32 %i12, i32 *%vptr
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store volatile i32 %i13, i32 *%vptr
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store volatile i32 %i14, i32 *%vptr
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ret void
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}
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