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ad5400fa72
for pre-2.9 bitcode files. We keep x86 unaligned loads, movnt, crc32, and the target indep prefetch change. As usual, updating the testsuite is a PITA. llvm-svn: 133337
34 lines
1.4 KiB
LLVM
34 lines
1.4 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | not grep fcpys
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; rdar://7117307
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%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
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%struct.List = type { %struct.List*, %struct.Patient*, %struct.List* }
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%struct.Patient = type { i32, i32, i32, %struct.Village* }
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%struct.Results = type { float, float, float }
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%struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 }
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define void @get_results(%struct.Results* noalias nocapture sret %agg.result, %struct.Village* %village) nounwind {
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entry:
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br i1 undef, label %bb, label %bb6.preheader
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bb6.preheader: ; preds = %entry
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 12, i32 4, i1 false)
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br i1 undef, label %bb15, label %bb13
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bb: ; preds = %entry
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ret void
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bb13: ; preds = %bb13, %bb6.preheader
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%0 = fadd float undef, undef ; <float> [#uses=1]
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%1 = fadd float undef, 1.000000e+00 ; <float> [#uses=1]
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br i1 undef, label %bb15, label %bb13
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bb15: ; preds = %bb13, %bb6.preheader
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%r1.0.0.lcssa = phi float [ 0.000000e+00, %bb6.preheader ], [ %1, %bb13 ] ; <float> [#uses=1]
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%r1.1.0.lcssa = phi float [ undef, %bb6.preheader ], [ %0, %bb13 ] ; <float> [#uses=0]
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store float %r1.0.0.lcssa, float* undef, align 4
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
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