Nikita Popov 609bfedb6b [InstCombine] Handle known shl nsw sign bit in SimplifyDemanded ... Ideally SimplifyDemanded should compute the same known bits as computeKnownBits(). This patch addresses one discrepancy, where ValueTracking is more powerful: If we have a shl nsw shift, we know that the sign bit of the input and output must be the same. If this results in a conflict, the result is poison. This is implemented in 2c4ca6832f/lib/Analysis/ValueTracking.cpp (L1175-L1179) and 2c4ca6832f/lib/Analysis/ValueTracking.cpp (L904-L908). This implements the same basic logic in SimplifyDemanded. It's slightly stronger, because I return undef instead of zero for the poison case (which is not an option inside ValueTracking). As mentioned in https://reviews.llvm.org/D75801#inline-698484, we could detect poison in more cases, this just establishes parity with the existing logic. Differential Revision: https://reviews.llvm.org/D76489		2020-03-20 18:16:05 +01:00
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Analysis	[InstCombine] Move test to instcombine; NFC	2020-03-20 12:41:19 +01:00
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CodeGen	[DAGCombiner] Do not fold truncate(build_vector(..)) if it creates an illegal type	2020-03-20 09:20:16 -07:00
DebugInfo	[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions	2020-03-19 15:35:16 -04:00
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MC	[WebAssembly] SIMD integer abs instructions	2020-03-19 17:25:58 -07:00
Object	[obj2yaml] - SHT_DYNAMIC and SHT_REL* sections: stop dumping sh_entsize field when it has the default value.	2020-03-19 17:25:53 +03:00
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tools	[llvm-readobj] Allow syms from all sections to match stack size entries	2020-03-20 10:54:18 +00:00
Transforms	[InstCombine] Handle known shl nsw sign bit in SimplifyDemanded	2020-03-20 18:16:05 +01:00
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Verifier	[VP,Integer,#1] Vector-predicated integer intrinsics	2020-03-19 10:51:47 +01:00
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