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72be097417
I'll work with Jim, Owen, and Bill on an alternative testing strategy until the assembly parser is available. llvm-svn: 117530
104 lines
5.1 KiB
LLVM
104 lines
5.1 KiB
LLVM
; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
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; XFAIL: *
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%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
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%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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; CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3]
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%tmp3 = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x2_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
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; CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3]
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%tmp5 = call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4)
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ret <8 x i8> %tmp5
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}
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define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x3_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
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; CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3]
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%tmp6 = call <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
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ret <8 x i8> %tmp6
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}
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define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x4_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
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; CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3]
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%tmp7 = call <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
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ret <8 x i8> %tmp7
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}
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define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = load <8 x i8>* %C
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; CHECK: vtbx.8 d18, {d16}, d17 @ encoding: [0xe1,0x28,0xf0,0xf3]
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%tmp4 = call <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
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ret <8 x i8> %tmp4
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}
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define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x2_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 1
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%tmp5 = load <8 x i8>* %C
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; CHECK: vtbx.8 d19, {d16, d17}, d18 @ encoding: [0xe2,0x39,0xf0,0xf3]
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%tmp6 = call <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
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ret <8 x i8> %tmp6
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}
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define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x3_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x3_t %tmp2, 2
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%tmp6 = load <8 x i8>* %C
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; CHECK: vtbx.8 d20, {d16, d17, d18}, d21 @ encoding: [0xe5,0x4a,0xf0,0xf3]
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%tmp7 = call <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
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ret <8 x i8> %tmp7
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}
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define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__neon_int8x8x4_t* %B
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%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 2
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%tmp6 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 3
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%tmp7 = load <8 x i8>* %C
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; CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 @ encoding: [0xe5,0x4b,0xf0,0xf3]
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%tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
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ret <8 x i8> %tmp8
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}
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declare <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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