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3a1cb40149
A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers. The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract the element from the vector instead. radar://13191881 llvm-svn: 175520
43 lines
1.3 KiB
LLVM
43 lines
1.3 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; PR12540: ARM backend lowering of FP_ROUND v2f64 to v2f32.
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define <2 x float> @vtrunc(<2 x double> %a) {
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; CHECK: vcvt.f32.f64 [[S0:s[0-9]+]], [[D0:d[0-9]+]]
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; CHECK: vcvt.f32.f64 [[S1:s[0-9]+]], [[D1:d[0-9]+]]
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%vt = fptrunc <2 x double> %a to <2 x float>
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ret <2 x float> %vt
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}
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define <2 x double> @vextend(<2 x float> %a) {
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; CHECK: vcvt.f64.f32 [[D0:d[0-9]+]], [[S0:s[0-9]+]]
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; CHECK: vcvt.f64.f32 [[D1:d[0-9]+]], [[S1:s[0-9]+]]
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%ve = fpext <2 x float> %a to <2 x double>
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ret <2 x double> %ve
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}
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; We used to generate vmovs between scalar and vfp/neon registers.
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; CHECK: vsitofp_double
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define void @vsitofp_double(<2 x i32>* %loadaddr,
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<2 x double>* %storeaddr) {
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%v0 = load <2 x i32>* %loadaddr
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; CHECK: vldr
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; CHECK-NEXT: vcvt.f64.s32
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; CHECK-NEXT: vcvt.f64.s32
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; CHECK-NEXT: vst
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%r = sitofp <2 x i32> %v0 to <2 x double>
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store <2 x double> %r, <2 x double>* %storeaddr
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ret void
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}
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; CHECK: vuitofp_double
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define void @vuitofp_double(<2 x i32>* %loadaddr,
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<2 x double>* %storeaddr) {
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%v0 = load <2 x i32>* %loadaddr
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; CHECK: vldr
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; CHECK-NEXT: vcvt.f64.u32
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; CHECK-NEXT: vcvt.f64.u32
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; CHECK-NEXT: vst
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%r = uitofp <2 x i32> %v0 to <2 x double>
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store <2 x double> %r, <2 x double>* %storeaddr
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ret void
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}
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