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https://github.com/RPCS3/llvm-mirror.git
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016eead73f
The (mostly-deprecated) SelectionDAG-based ILPListDAGScheduler scheduler was making poor scheduling decisions, causing high register pressure and extraneous register spills. Switching to the newer machine scheduler generates better code -- even without there being a machine model defined for SPARC yet. (Actually committing the test changes too, this time, unlike r247315) llvm-svn: 247343
77 lines
2.3 KiB
LLVM
77 lines
2.3 KiB
LLVM
; RUN: llc < %s -disable-block-placement | FileCheck %s
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; RUN: llc < %s -disable-block-placement -disable-sparc-leaf-proc=0 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"
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target triple = "sparcv9-sun-solaris"
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; CHECK: varargsfunc
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; 128 byte save ares + 1 alloca rounded up to 16 bytes alignment.
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; CHECK: save %sp, -144, %sp
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; Store the ... arguments to the argument array. The order is not important.
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; CHECK: stx %i5, [%fp+2215]
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; CHECK: stx %i4, [%fp+2207]
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; CHECK: stx %i3, [%fp+2199]
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; CHECK: stx %i2, [%fp+2191]
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; Store the address of the ... args to %ap at %fp+BIAS+128-8
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; add %fp, 2191, [[R:[gilo][0-7]]]
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; stx [[R]], [%fp+2039]
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define double @varargsfunc(i8* nocapture %fmt, double %sum, ...) {
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entry:
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%ap = alloca i8*, align 4
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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br label %for.cond
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for.cond:
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%fmt.addr.0 = phi i8* [ %fmt, %entry ], [ %incdec.ptr, %for.cond.backedge ]
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%sum.addr.0 = phi double [ %sum, %entry ], [ %sum.addr.0.be, %for.cond.backedge ]
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%incdec.ptr = getelementptr inbounds i8, i8* %fmt.addr.0, i64 1
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%0 = load i8, i8* %fmt.addr.0, align 1
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%conv = sext i8 %0 to i32
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switch i32 %conv, label %sw.default [
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i32 105, label %sw.bb
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i32 102, label %sw.bb3
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]
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; CHECK: sw.bb
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; ldx [%fp+2039], %[[AP:[gilo][0-7]]]
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; add %[[AP]], 4, %[[AP2:[gilo][0-7]]]
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; stx %[[AP2]], [%fp+2039]
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; ld [%[[AP]]]
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sw.bb:
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%1 = va_arg i8** %ap, i32
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%conv2 = sitofp i32 %1 to double
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br label %for.cond.backedge
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; CHECK: sw.bb3
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; ldx [%fp+2039], %[[AP:[gilo][0-7]]]
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; add %[[AP]], 8, %[[AP2:[gilo][0-7]]]
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; stx %[[AP2]], [%fp+2039]
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; ldd [%[[AP]]]
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sw.bb3:
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%2 = va_arg i8** %ap, double
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br label %for.cond.backedge
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for.cond.backedge:
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%.pn = phi double [ %2, %sw.bb3 ], [ %conv2, %sw.bb ]
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%sum.addr.0.be = fadd double %.pn, %sum.addr.0
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br label %for.cond
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sw.default:
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ret double %sum.addr.0
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}
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declare void @llvm.va_start(i8*)
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@.str = private unnamed_addr constant [4 x i8] c"abc\00", align 1
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; CHECK: call_1d
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; The fixed-arg double goes in %d2, the second goes in %o2.
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; CHECK: sethi 1048576
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; CHECK: , %f2
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; CHECK: , %o2
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define i32 @call_1d() #0 {
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entry:
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%call = call double (i8*, double, ...) @varargsfunc(i8* undef, double 1.000000e+00, double 2.000000e+00)
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ret i32 1
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}
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