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b7a99b0894
This patch changes the location of the frame-record (FP, LR) to the
bottom of the callee-saved area. According to the AAPCS the location of
the frame-record within the stackframe is unspecified (section 5.2.3 The
Frame Pointer), so the compiler should be free to choose a different
location.
The reason for changing the location of the frame-record is to prepare
the frame for allocating an SVE area below the callee-saves. This way the
compiler can use the VL-scaled addressing modes to directly access SVE
objects from the frame-pointer.
: :
| stack | | stack |
| args | | args |
+-------+ +-------+
| x30 | | x19 |
| x29 | | x20 |
FP -> |- - - -| | x21 |
| x19 | ==> | x22 |
| x20 | |- - - -|
| x21 | | x30 |
| x22 | | x29 |
+-------+ +-------+ <- FP
|///////| |///////| // realignment gap
|- - - -| |- - - -|
|spills/| |spills/|
| locals| | locals|
SP -> +-------+ +-------+ <- SP
Things to point out:
- The algorithm to find a paired register should be prevented from
accidentally pairing some callee-saved register with LR that is not
FP, since they should always be paired together when the frame
has a frame-record.
- For Darwin platforms the location of the frame-record is unchanged,
since the unwind encoding does not allow for encoding this position
dynamically and other tools currently depend on the former layout.
Reviewers: efriedma, rovka, rengolin, thegameg, greened, t.p.northover
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D65653
llvm-svn: 368987
28 lines
865 B
LLVM
28 lines
865 B
LLVM
; RUN: llc -mtriple=arm64-eabi -mcpu=cyclone < %s | FileCheck %s
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; CHECK: foo
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; CHECK-DAG: str w[[REG0:[0-9]+]], [x29, #24]
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; CHECK-DAG: str w[[REG0]], [x29, #28]
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define i32 @foo(i32 %a) nounwind {
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%retval = alloca i32, align 4
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%a.addr = alloca i32, align 4
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%arr = alloca [32 x i32], align 4
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%i = alloca i32, align 4
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%arr2 = alloca [32 x i32], align 4
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%j = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%tmp = load i32, i32* %a.addr, align 4
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%tmp1 = zext i32 %tmp to i64
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%v = mul i64 4, %tmp1
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%vla = alloca i8, i64 %v, align 4
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%tmp2 = bitcast i8* %vla to i32*
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%tmp3 = load i32, i32* %a.addr, align 4
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store i32 %tmp3, i32* %i, align 4
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%tmp4 = load i32, i32* %a.addr, align 4
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store i32 %tmp4, i32* %j, align 4
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%tmp5 = load i32, i32* %j, align 4
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store i32 %tmp5, i32* %retval
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%x = load i32, i32* %retval
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ret i32 %x
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}
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