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b7ab6fd782
The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. llvm-svn: 182920
50 lines
1.5 KiB
LLVM
50 lines
1.5 KiB
LLVM
; Make sure that the alloca offset isn't lost when the alloca result is
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; used directly in a load or store. There must always be an LA or LAY.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-D
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declare i64 @bar(i8 *%a)
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define i64 @f1(i64 %length, i64 %index) {
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; CHECK-A: f1:
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; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]]
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; CHECK-A: la %r2, 160([[ADDR]])
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; CHECK-A: mvi 0(%r2), 0
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;
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; CHECK-B: f1:
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; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]]
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; CHECK-B: la %r2, 160([[ADDR]])
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; CHECK-B: mvi 4095(%r2), 1
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;
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; CHECK-C: f1:
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; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
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; CHECK-C: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
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; CHECK-C: mvi 0([[TMP]]), 2
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;
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; CHECK-D: f1:
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; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
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; CHECK-D: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
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; CHECK-D: mvi 4095([[TMP]]), 3
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;
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; CHECK-E: f1:
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; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
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; CHECK-E: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
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; CHECK-E: mviy 4096([[TMP]]), 4
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%a = alloca i8, i64 %length
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store volatile i8 0, i8 *%a
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%b = getelementptr i8 *%a, i64 4095
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store volatile i8 1, i8 *%b
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%c = getelementptr i8 *%a, i64 %index
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store volatile i8 2, i8 *%c
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%d = getelementptr i8 *%c, i64 4095
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store volatile i8 3, i8 *%d
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%e = getelementptr i8 *%d, i64 1
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store volatile i8 4, i8 *%e
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%count = call i64 @bar(i8 *%a)
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%res = add i64 %count, 1
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ret i64 %res
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}
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