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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 20:43:44 +02:00
llvm-mirror/test/CodeGen
Elena Demikhovsky 45e0f9e6b6 AVX512: combining setcc and zext is wrong on AVX512
because vector compare instruction puts result in mask register.

llvm-svn: 199798
2014-01-22 12:26:19 +00:00
..
AArch64 [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or SHUFFLE_VECTOR. 2014-01-22 06:11:03 +00:00
ARM Remove the useless pseudo instructions VDUPfdf and VDUPfqf, replacing them with patterns to match VDUPLN. 2014-01-20 17:14:48 +00:00
CPP Begin adding docs and IR-level support for the inalloca attribute 2013-12-19 02:14:12 +00:00
Generic Remove a failing test to get the buildbots back to green. 2014-01-06 00:43:09 +00:00
Hexagon
Inputs
Mips Fix PR18572 - llc crash during GenericScheduler::initPolicy(). 2014-01-21 21:27:37 +00:00
MSP430
NVPTX [NVPTX] Add missing patterns for div.approx with immediate denominator 2014-01-21 14:40:05 +00:00
PowerPC Fix pointer info on PPC byval stores 2014-01-21 20:15:58 +00:00
R600 Fix broken CHECK lines. 2014-01-11 21:06:00 +00:00
SPARC [Sparc] Add support for inline assembly constraints which specify registers by their aliases. 2014-01-22 03:18:42 +00:00
SystemZ [SystemZ] Flesh out stackrestore test (frame-11.ll) 2014-01-13 15:44:44 +00:00
Thumb CodeGen: Stop treating vectors as aggregates 2014-01-21 22:46:46 +00:00
Thumb2 Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks 2014-01-13 18:47:54 +00:00
X86 AVX512: combining setcc and zext is wrong on AVX512 2014-01-22 12:26:19 +00:00
XCore Fix broken CHECK lines. 2014-01-11 21:06:00 +00:00