Matt Arsenault b7fa1ffa8b AMDGPU: Use assert zext for workgroup sizes ... llvm-svn: 254328		2015-11-30 21:15:45 +00:00
..
AArch64	[CodeGenPrepare] Create more extloads and fewer ands	2015-11-20 22:34:39 +00:00
AMDGPU	AMDGPU: Use assert zext for workgroup sizes	2015-11-30 21:15:45 +00:00
ARM	[ARM] For old thumb ISA like v4t, we cannot use PC directly in pop.	2015-11-30 20:37:58 +00:00
BPF	Revert "Change memcpy/memset/memmove to have dest and source alignments."	2015-11-19 05:56:52 +00:00
CPP
Generic	Let SelectionDAG start to use probability-based interface to add successors.	2015-11-24 08:51:23 +00:00
Hexagon	[Hexagon] Hexagon V60 HVX intrinsic defintions	2015-11-26 16:54:33 +00:00
Inputs
Mips	[mips][ias] Explicitly disable IAS on tests that depend on not assembling.	2015-11-26 11:23:03 +00:00
MIR	MachineVerifier: Add missing linebreak	2015-11-09 23:59:29 +00:00
MSP430	Revert "Change memcpy/memset/memmove to have dest and source alignments."	2015-11-19 05:56:52 +00:00
NVPTX	Have a single way for creating unique value names.	2015-11-22 00:16:24 +00:00
PowerPC	Enable shrink wrapping for PPC64	2015-11-30 18:59:41 +00:00
SPARC
SystemZ	llvm/test/CodeGen/SystemZ/alloca-04.ll REQUIRES asserts due to -debug-pass.	2015-11-28 13:05:49 +00:00
Thumb	Revert "Change memcpy/memset/memmove to have dest and source alignments."	2015-11-19 05:56:52 +00:00
Thumb2	Fix test case label check	2015-11-20 20:24:49 +00:00
WebAssembly	[WebAssembly] Fix inline asm support for i64 operands.	2015-11-25 22:28:50 +00:00
WinEH	[WinEH] Disable most forms of demotion	2015-11-19 23:23:33 +00:00
X86	[X86] Add RIP to GR64_TCW64	2015-11-30 19:04:19 +00:00
XCore	Revert "Change memcpy/memset/memmove to have dest and source alignments."	2015-11-19 05:56:52 +00:00