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fedbc49000
Summary: As part of this, define DenseMapInfo for MCRegister (and Register while I'm at it) Depends on D65599 Reviewers: arsenm Subscribers: MatzeB, qcolombet, jvesely, wdng, nhaehnle, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65605 llvm-svn: 367719
137 lines
5.0 KiB
C++
137 lines
5.0 KiB
C++
//===- MC/MCRegisterInfo.cpp - Target Register Description ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements MCRegisterInfo functions.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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MCRegister
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MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
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const MCRegisterClass *RC) const {
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for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
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if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
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return *Supers;
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return 0;
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}
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MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const {
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assert(Idx && Idx < getNumSubRegIndices() &&
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"This is not a subregister index");
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// Get a pointer to the corresponding SubRegIndices list. This list has the
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// name of each sub-register in the same order as MCSubRegIterator.
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const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
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for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
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if (*SRI == Idx)
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return *Subs;
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return 0;
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}
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unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg,
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MCRegister SubReg) const {
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assert(SubReg && SubReg < getNumRegs() && "This is not a register");
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// Get a pointer to the corresponding SubRegIndices list. This list has the
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// name of each sub-register in the same order as MCSubRegIterator.
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const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
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for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
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if (*Subs == SubReg)
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return *SRI;
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return 0;
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}
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unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
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assert(Idx && Idx < getNumSubRegIndices() &&
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"This is not a subregister index");
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return SubRegIdxRanges[Idx].Size;
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}
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unsigned MCRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
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assert(Idx && Idx < getNumSubRegIndices() &&
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"This is not a subregister index");
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return SubRegIdxRanges[Idx].Offset;
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}
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int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
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const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
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unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
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if (!M)
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return -1;
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DwarfLLVMRegPair Key = { RegNum, 0 };
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const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
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if (I == M+Size || I->FromReg != RegNum)
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return -1;
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return I->ToReg;
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}
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int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
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const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
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unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
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if (!M)
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return -1;
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DwarfLLVMRegPair Key = { RegNum, 0 };
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const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
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assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum");
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return I->ToReg;
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}
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int MCRegisterInfo::getLLVMRegNumFromEH(unsigned RegNum) const {
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const DwarfLLVMRegPair *M = EHDwarf2LRegs;
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unsigned Size = EHDwarf2LRegsSize;
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if (!M)
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return -1;
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DwarfLLVMRegPair Key = { RegNum, 0 };
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const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
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if (I == M+Size || I->FromReg != RegNum)
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return -1;
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return I->ToReg;
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}
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int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const {
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// On ELF platforms, DWARF EH register numbers are the same as DWARF
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// other register numbers. On Darwin x86, they differ and so need to be
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// mapped. The .cfi_* directives accept integer literals as well as
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// register names and should generate exactly what the assembly code
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// asked for, so there might be DWARF/EH register numbers that don't have
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// a corresponding LLVM register number at all. So if we can't map the
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// EH register number to an LLVM register number, assume it's just a
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// valid DWARF register number as is.
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int LRegNum = getLLVMRegNumFromEH(RegNum);
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if (LRegNum != -1)
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return getDwarfRegNum(LRegNum, false);
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return RegNum;
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}
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int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const {
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const DenseMap<MCRegister, int>::const_iterator I = L2SEHRegs.find(RegNum);
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if (I == L2SEHRegs.end()) return (int)RegNum;
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return I->second;
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}
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int MCRegisterInfo::getCodeViewRegNum(MCRegister RegNum) const {
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if (L2CVRegs.empty())
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report_fatal_error("target does not implement codeview register mapping");
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const DenseMap<MCRegister, int>::const_iterator I = L2CVRegs.find(RegNum);
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if (I == L2CVRegs.end())
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report_fatal_error("unknown codeview register " + (RegNum < getNumRegs()
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? getName(RegNum)
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: Twine(RegNum)));
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return I->second;
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}
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