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bf35274368
. "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode. . Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode. . Consequently, the conversion produces incorrect numbers. The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows. The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). llvm-svn: 149056
84 lines
2.0 KiB
LLVM
84 lines
2.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: vcvtdq2ps %ymm
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define <8 x float> @sitofp00(<8 x i32> %a) nounwind {
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%b = sitofp <8 x i32> %a to <8 x float>
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ret <8 x float> %b
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}
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; CHECK: vcvttps2dq %ymm
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define <8 x i32> @fptosi00(<8 x float> %a) nounwind {
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%b = fptosi <8 x float> %a to <8 x i32>
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ret <8 x i32> %b
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}
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; CHECK: vcvtdq2pd %xmm
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define <4 x double> @sitofp01(<4 x i32> %a) {
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%b = sitofp <4 x i32> %a to <4 x double>
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ret <4 x double> %b
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}
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; CHECK: vcvttpd2dqy %ymm
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define <4 x i32> @fptosi01(<4 x double> %a) {
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%b = fptosi <4 x double> %a to <4 x i32>
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ret <4 x i32> %b
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}
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; CHECK: vcvtpd2psy %ymm
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; CHECK-NEXT: vcvtpd2psy %ymm
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; CHECK-NEXT: vinsertf128 $1
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define <8 x float> @fptrunc00(<8 x double> %b) nounwind {
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%a = fptrunc <8 x double> %b to <8 x float>
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ret <8 x float> %a
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}
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; CHECK: vcvtps2pd %xmm
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define <4 x double> @fpext00(<4 x float> %b) nounwind {
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%a = fpext <4 x float> %b to <4 x double>
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ret <4 x double> %a
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}
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; CHECK: vcvtsi2sdq (%
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define double @funcA(i64* nocapture %e) nounwind uwtable readonly ssp {
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entry:
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%tmp1 = load i64* %e, align 8
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%conv = sitofp i64 %tmp1 to double
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ret double %conv
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}
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; CHECK: vcvtsi2sd (%
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define double @funcB(i32* nocapture %e) nounwind uwtable readonly ssp {
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entry:
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%tmp1 = load i32* %e, align 4
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%conv = sitofp i32 %tmp1 to double
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ret double %conv
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}
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; CHECK: vcvtsi2ss (%
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define float @funcC(i32* nocapture %e) nounwind uwtable readonly ssp {
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entry:
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%tmp1 = load i32* %e, align 4
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%conv = sitofp i32 %tmp1 to float
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ret float %conv
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}
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; CHECK: vcvtsi2ssq (%
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define float @funcD(i64* nocapture %e) nounwind uwtable readonly ssp {
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entry:
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%tmp1 = load i64* %e, align 8
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%conv = sitofp i64 %tmp1 to float
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ret float %conv
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}
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; CHECK: vcvtss2sd
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define void @fpext() nounwind uwtable {
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entry:
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%f = alloca float, align 4
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%d = alloca double, align 8
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%tmp = load float* %f, align 4
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%conv = fpext float %tmp to double
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store double %conv, double* %d, align 8
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ret void
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}
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