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98be3942ed
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. llvm-svn: 216225
20 lines
656 B
LLVM
20 lines
656 B
LLVM
; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
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; Test if the BBs are reordred according to their branch weights.
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define i64 @branch_weights_test(i64 %a, i64 %b) {
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; CHECK-LABEL: branch_weights_test
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; CHECK-LABEL: success
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; CHECK-LABEL: fail
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%1 = icmp ult i64 %a, %b
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br i1 %1, label %fail, label %success, !prof !0
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fail:
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ret i64 -1
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success:
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ret i64 0
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}
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!0 = metadata !{metadata !"branch_weights", i32 0, i32 2147483647}
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