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4c4a37be92
This is the groundwork for adding the Armv8.2-A FP16 vector intrinsics, which uses v4f16 and v8f16 vector operands and return values. All the moving parts are tested with two intrinsics, a 1-operand v8f16 and a 2-operand v4f16 intrinsic. In a follow-up patch the rest of the intrinsics and tests will be added. Differential Revision: https://reviews.llvm.org/D44538 llvm-svn: 327839
22 lines
857 B
LLVM
22 lines
857 B
LLVM
; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+v8.2a,+fullfp16,+neon -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-HARD
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+v8.2a,+fullfp16,+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP
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declare <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half>, <4 x half>)
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define dso_local <4 x half> @t_vpadd_f16(<4 x half> %a, <4 x half> %b) {
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; CHECK: t_vpadd_f16:
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; CHECK-HARD: vpadd.f16 d0, d0, d1
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; CHECK-HARD-NEXT: bx lr
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; CHECK-SOFTFP: vmov [[D1:d[0-9]+]], r2, r3
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; CHECK-SOFTFP: vmov [[D2:d[0-9]+]], r0, r1
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; CHECK-SOFTFP: vpadd.f16 [[D3:d[0-9]+]], [[D2]], [[D1]]
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; CHECK-SOFTFP: vmov r0, r1, [[D3]]
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; CHECK-SOFTFP: bx lr
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entry:
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%vpadd_v2.i = tail call <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half> %a, <4 x half> %b)
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ret <4 x half> %vpadd_v2.i
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}
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