Andrea Di Biagio 4893e095df [llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register. ... This patch teaches llvm-mca how to identify register writes that implicitly zero the upper portion of a super-register. On X86-64, a general purpose register is implemented in hardware as a 64-bit register. Quoting the Intel 64 Software Developer's Manual: "an update to the lower 32 bits of a 64 bit integer register is architecturally defined to zero extend the upper 32 bits". Also, a write to an XMM register performed by an AVX instruction implicitly zeroes the upper 128 bits of the aliasing YMM register. This patch adds a new method named clearsSuperRegisters to the MCInstrAnalysis interface to help identify instructions that implicitly clear the upper portion of a super-register. The rest of the patch teaches llvm-mca how to use that new method to obtain the information, and update the register dependencies accordingly. I compared the kernels from tests clear-super-register-1.s and clear-super-register-2.s against the output from perf on btver2. Previously there was a large discrepancy between the estimated IPC and the measured IPC. Now the differences are mostly in the noise. Differential Revision: https://reviews.llvm.org/D48225 llvm-svn: 335113		2018-06-20 10:08:11 +00:00
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AArch64	[CodeGen] assume max/default throughput for unspecified instructions	2018-06-05 23:34:45 +00:00
ARM	[llvm-mca] Regenerate a test to remove a double newline	2018-06-04 12:30:03 +00:00
X86	[llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register.	2018-06-20 10:08:11 +00:00
invalid_input_file_name.test
lit.local.cfg