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42e0928a60
There is not match for the `MipsJmpLink texternalsym` and `MipsJmpLink tglobaladdr` patterns for microMIPS R6. As a result LLVM incorrectly selects the `JALRC16` compact 2-byte instruction which takes a target instruction address from a register only and assign `R_MIPS_32` relocation for this instruction. This relocation completely overwrites `JALRC16` and nearby instructions. This patch adds missed matching patterns, selects `BALC` instruction and assign a correct `R_MICROMIPS_PC26_S1` relocation. Differential Revision: https://reviews.llvm.org/D64552 llvm-svn: 365870
23 lines
642 B
LLVM
23 lines
642 B
LLVM
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
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; RUN: -relocation-model=static -O2 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \
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; RUN: -relocation-model=static -O2 < %s | FileCheck %s -check-prefix=CHECK-MMR6
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; Function Attrs: nounwind
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define i32 @foo(i32 signext %a) #0 {
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entry:
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%0 = load i32, i32* %a.addr, align 4
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%shl = shl i32 %0, 2
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%call = call i32 @bar(i32 signext %shl)
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ret i32 %call
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}
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declare i32 @bar(i32 signext) #1
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; CHECK: jals
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; CHECK-NEXT: sll16
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; CHECK-MMR6: balc
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; CHECK-MMR6-NOT: sll16
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