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4d1afff4de
Filling a delay slot in 32bit jump instructions with a 16bit instruction can cause issues. According to the documentation such an operation is unpredictable. This patch adds opcode Mips::PseudoIndirectBranch_MM alongside Mips::PseudoIndirectBranch and other instructions that are expanded to jr instruction and do not allow a 16bit instruction in their delay slots. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D58507 llvm-svn: 354672
69 lines
1.9 KiB
LLVM
69 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+micromips -relocation-model=pic < %s | FileCheck %s
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; Test that the delay slot filler correctly handles indirect branches for
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; microMIPS in regard to incorrectly using 16bit instructions in delay slots of
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; 32bit instructions.
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define i32 @test(i32 signext %x, i32 signext %c) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui $2, %hi(_gp_disp)
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; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)
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; CHECK-NEXT: addiur2 $5, $5, -1
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; CHECK-NEXT: sltiu $1, $5, 4
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; CHECK-NEXT: beqz $1, $BB0_3
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; CHECK-NEXT: addu $3, $2, $25
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; CHECK-NEXT: $BB0_1: # %entry
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; CHECK-NEXT: li16 $2, 0
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; CHECK-NEXT: sll16 $5, $5, 2
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; CHECK-NEXT: lw $6, %got($JTI0_0)($3)
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; CHECK-NEXT: addu16 $5, $5, $6
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; CHECK-NEXT: lw $5, %lo($JTI0_0)($5)
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; CHECK-NEXT: addu16 $3, $5, $3
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; CHECK-NEXT: jr $3
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; CHECK-NEXT: nop
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; CHECK-NEXT: $BB0_2: # %sw.bb2
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; CHECK-NEXT: addiur2 $2, $4, 1
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; CHECK-NEXT: jrc $ra
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; CHECK-NEXT: $BB0_3:
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; CHECK-NEXT: move $2, $4
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; CHECK-NEXT: jrc $ra
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; CHECK-NEXT: $BB0_4: # %sw.bb3
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; CHECK-NEXT: addius5 $4, 2
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; CHECK-NEXT: move $2, $4
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; CHECK-NEXT: jrc $ra
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; CHECK-NEXT: $BB0_5: # %sw.bb5
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; CHECK-NEXT: addius5 $4, 3
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; CHECK-NEXT: move $2, $4
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; CHECK-NEXT: $BB0_6: # %for.cond.cleanup
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; CHECK-NEXT: jrc $ra
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entry:
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switch i32 %c, label %sw.epilog [
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i32 4, label %sw.bb5
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i32 1, label %for.cond.cleanup
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i32 2, label %sw.bb2
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i32 3, label %sw.bb3
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]
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sw.bb2:
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%add = add nsw i32 %x, 1
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br label %sw.epilog
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sw.bb3:
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%add4 = add nsw i32 %x, 2
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br label %sw.epilog
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sw.bb5:
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%add6 = add nsw i32 %x, 3
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br label %sw.epilog
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sw.epilog:
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%a.0 = phi i32 [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add, %sw.bb2 ], [ %x, %entry ]
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br label %for.cond.cleanup
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for.cond.cleanup:
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%a.028 = phi i32 [ %a.0, %sw.epilog ], [ 0, %entry ]
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ret i32 %a.028
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}
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