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dad6c47e6b
This is step 1 of unknown towards fixing PR28001: https://llvm.org/bugs/show_bug.cgi?id=28001 llvm-svn: 271810
26 lines
736 B
LLVM
26 lines
736 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; Convert the zext+slt into a simple ult.
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define i1 @scalar_zext_slt(i16 %t4) {
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; CHECK-LABEL: @scalar_zext_slt(
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; CHECK-NEXT: [[T6:%.*]] = icmp ult i16 %t4, 500
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; CHECK-NEXT: ret i1 [[T6]]
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;
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%t5 = zext i16 %t4 to i32
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%t6 = icmp slt i32 %t5, 500
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ret i1 %t6
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}
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define <4 x i1> @vector_zext_slt(<4 x i16> %t4) {
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; CHECK-LABEL: @vector_zext_slt(
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; CHECK-NEXT: [[T6:%.*]] = icmp ult <4 x i16> %t4, <i16 500, i16 0, i16 501, i16 -1>
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; CHECK-NEXT: ret <4 x i1> [[T6]]
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;
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%t5 = zext <4 x i16> %t4 to <4 x i32>
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%t6 = icmp slt <4 x i32> %t5, <i32 500, i32 0, i32 501, i32 65535>
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ret <4 x i1> %t6
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}
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