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https://github.com/RPCS3/llvm-mirror.git
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b902c71a90
llvm-svn: 75923
120 lines
3.9 KiB
C++
120 lines
3.9 KiB
C++
//===- SystemZRegisterInfo.cpp - SystemZ Register Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SystemZ implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "SystemZRegisterInfo.h"
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#include "SystemZSubtarget.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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using namespace llvm;
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SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
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const TargetInstrInfo &tii)
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: SystemZGenRegisterInfo(SystemZ::NOP, SystemZ::NOP),
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TM(tm), TII(tii) {
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}
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const unsigned*
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SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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static const unsigned CalleeSavedRegs[] = {
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SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D,
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SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
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SystemZ::F1, SystemZ::F3, SystemZ::F5, SystemZ::F7,
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0
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};
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return CalleeSavedRegs;
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}
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const TargetRegisterClass* const*
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SystemZRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
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static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
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&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
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&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
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&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
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&SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
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&SystemZ::FP64RegClass, &SystemZ::FP64RegClass,
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&SystemZ::FP64RegClass, &SystemZ::FP64RegClass, 0
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};
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return CalleeSavedRegClasses;
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}
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BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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if (hasFP(MF))
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Reserved.set(SystemZ::R11D);
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Reserved.set(SystemZ::R14D);
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Reserved.set(SystemZ::R15D);
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return Reserved;
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}
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// needsFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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bool SystemZRegisterInfo::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return NoFramePointerElim || MFI->hasVarSizedObjects();
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}
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void SystemZRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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assert(0 && "Not implemented yet!");
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}
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void SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const {
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assert(0 && "Not implemented yet!");
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}
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void SystemZRegisterInfo::emitPrologue(MachineFunction &MF) const {
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// Nothing here yet
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}
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void SystemZRegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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// Nothing here yet
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}
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unsigned SystemZRegisterInfo::getRARegister() const {
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assert(0 && "What is the return address register");
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return 0;
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}
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unsigned SystemZRegisterInfo::getFrameRegister(MachineFunction &MF) const {
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assert(0 && "What is the frame register");
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return 0;
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}
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unsigned SystemZRegisterInfo::getEHExceptionRegister() const {
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assert(0 && "What is the exception register");
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return 0;
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}
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unsigned SystemZRegisterInfo::getEHHandlerRegister() const {
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assert(0 && "What is the exception handler register");
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return 0;
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}
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int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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assert(0 && "What is the dwarf register number");
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return -1;
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}
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#include "SystemZGenRegisterInfo.inc"
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