mirror of
https://github.com/RPCS3/llvm-mirror.git
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564945a3af
Add assembler support for all atomic instructions that weren't already supported. Some of those could be used to implement codegen for 128-bit atomic operations, but this isn't done here yet. llvm-svn: 288526
770 lines
31 KiB
TableGen
770 lines
31 KiB
TableGen
//=- SystemZScheduleZ196.td - SystemZ Scheduling Definitions ---*- tblgen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for Z196 to support instruction
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// scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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def Z196Model : SchedMachineModel {
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let UnsupportedFeatures = Arch9UnsupportedFeatures.List;
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let IssueWidth = 5;
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let MicroOpBufferSize = 40; // Issue queues
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let LoadLatency = 1; // Optimistic load latency.
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let PostRAScheduler = 1;
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// Extra cycles for a mispredicted branch.
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let MispredictPenalty = 16;
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}
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let SchedModel = Z196Model in {
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// These definitions could be put in a subtarget common include file,
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// but it seems the include system in Tablegen currently rejects
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// multiple includes of same file.
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def : WriteRes<GroupAlone, []> {
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let NumMicroOps = 0;
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let BeginGroup = 1;
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let EndGroup = 1;
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}
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def : WriteRes<EndGroup, []> {
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let NumMicroOps = 0;
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let EndGroup = 1;
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}
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def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
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def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
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def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
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def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
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def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
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def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
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def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
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def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
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def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
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def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
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def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
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def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
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def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
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def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
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// Execution units.
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def Z196_FXUnit : ProcResource<2>;
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def Z196_LSUnit : ProcResource<2>;
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def Z196_FPUnit : ProcResource<1>;
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// Subtarget specific definitions of scheduling resources.
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def : WriteRes<FXU, [Z196_FXUnit]> { let Latency = 1; }
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def : WriteRes<LSU, [Z196_LSUnit]> { let Latency = 4; }
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def : WriteRes<LSU_lat1, [Z196_LSUnit]> { let Latency = 1; }
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def : WriteRes<FPU, [Z196_FPUnit]> { let Latency = 8; }
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def : WriteRes<FPU2, [Z196_FPUnit, Z196_FPUnit]> { let Latency = 9; }
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// -------------------------- INSTRUCTIONS ---------------------------------- //
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// InstRW constructs have been used in order to preserve the
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// readability of the InstrInfo files.
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// For each instruction, as matched by a regexp, provide a list of
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// resources that it needs. These will be combined into a SchedClass.
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//===----------------------------------------------------------------------===//
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// Stack allocation
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
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//===----------------------------------------------------------------------===//
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// Branch instructions
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//===----------------------------------------------------------------------===//
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// Branch
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def : InstRW<[LSU, EndGroup], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
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def : InstRW<[LSU, EndGroup], (instregex "(Call)?J(G)?(Asm.*)?$")>;
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def : InstRW<[LSU, EndGroup], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
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def : InstRW<[LSU, EndGroup], (instregex "(Call)?B(R)?(Asm.*)?$")>;
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def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BRCT(G|H)?$")>;
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def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BCT(G)?(R)?$")>;
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def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone],
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(instregex "B(R)?X(H|L).*$")>;
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// Compare and branch
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def : InstRW<[FXU, LSU, Lat5, GroupAlone],
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(instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
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def : InstRW<[FXU, LSU, Lat5, GroupAlone],
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(instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
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//===----------------------------------------------------------------------===//
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// Trap instructions
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//===----------------------------------------------------------------------===//
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// Trap
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def : InstRW<[LSU, EndGroup], (instregex "(Cond)?Trap$")>;
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// Compare and trap
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def : InstRW<[FXU], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
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def : InstRW<[FXU], (instregex "CL(G)?RT(Asm.*)?$")>;
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def : InstRW<[FXU], (instregex "CL(F|G)IT(Asm.*)?$")>;
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//===----------------------------------------------------------------------===//
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// Call and return instructions
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//===----------------------------------------------------------------------===//
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// Call
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def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRAS$")>;
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def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
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def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
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def : InstRW<[LSU, FXU, FXU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
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// Return
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def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
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def : InstRW<[LSU_lat1, EndGroup], (instregex "CondReturn$")>;
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//===----------------------------------------------------------------------===//
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// Select instructions
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//===----------------------------------------------------------------------===//
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// Select pseudo
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def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
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// CondStore pseudos
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def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
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def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
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def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
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def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
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def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
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def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
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//===----------------------------------------------------------------------===//
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// Move instructions
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//===----------------------------------------------------------------------===//
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// Moves
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def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
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// Move character
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def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
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// Pseudo -> reg move
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def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
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def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
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def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
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def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
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def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
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// Loads
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def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
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def : InstRW<[LSU], (instregex "LG(RL)?$")>;
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def : InstRW<[LSU], (instregex "L128$")>;
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def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
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def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
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def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
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def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
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def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
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// Load and test
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def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
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def : InstRW<[FXU], (instregex "LT(G)?R$")>;
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// Stores
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def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
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// String moves.
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
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//===----------------------------------------------------------------------===//
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// Conditional move instructions
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, Lat2, EndGroup], (instregex "LOC(G)?R(Asm.*)?$")>;
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def : InstRW<[FXU, LSU, Lat6, EndGroup], (instregex "LOC(G)?(Asm.*)?$")>;
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def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "STOC(G)?(Asm.*)?$")>;
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//===----------------------------------------------------------------------===//
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// Sign extensions
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
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def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
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def : InstRW<[FXU], (instregex "LTGFR$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
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//===----------------------------------------------------------------------===//
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// Zero extensions
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
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def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
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def : InstRW<[FXU], (instregex "LLG(C|F|H|T)R$")>;
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def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
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def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
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def : InstRW<[LSU], (instregex "LLHRL$")>;
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def : InstRW<[LSU], (instregex "LLG(C|F|H|T|FRL|HRL)$")>;
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//===----------------------------------------------------------------------===//
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// Truncations
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
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//===----------------------------------------------------------------------===//
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// Multi-register moves
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//===----------------------------------------------------------------------===//
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// Load multiple (estimated average of 5 ops)
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def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
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(instregex "LM(H|Y|G)?$")>;
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// Store multiple (estimated average of 3 ops)
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def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
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(instregex "STM(H|Y|G)?$")>;
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//===----------------------------------------------------------------------===//
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// Byte swaps
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
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//===----------------------------------------------------------------------===//
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// Load address instructions
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
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// Load the Global Offset Table address
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def : InstRW<[FXU], (instregex "GOT$")>;
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//===----------------------------------------------------------------------===//
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// Absolute and Negation
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
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def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
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def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
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def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
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def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
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//===----------------------------------------------------------------------===//
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// Insertion
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
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def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
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def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
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def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
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def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
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def : InstRW<[FXU], (instregex "IILF(64)?$")>;
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def : InstRW<[FXU], (instregex "IILH(64)?$")>;
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def : InstRW<[FXU], (instregex "IILL(64)?$")>;
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//===----------------------------------------------------------------------===//
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// Addition
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
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def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AH(Y)?$")>;
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def : InstRW<[FXU], (instregex "AIH$")>;
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def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
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def : InstRW<[FXU], (instregex "AGFI$")>;
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def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
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def : InstRW<[FXU], (instregex "AGR(K)?$")>;
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def : InstRW<[FXU], (instregex "AHI(K)?$")>;
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def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
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def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
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def : InstRW<[FXU], (instregex "ALGHSIK$")>;
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def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
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def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
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def : InstRW<[FXU], (instregex "ALR(K)?$")>;
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def : InstRW<[FXU], (instregex "AR(K)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
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// Logical addition with carry
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def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
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def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
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// Add with sign extension (32 -> 64)
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def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "AGF$")>;
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def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "AGFR$")>;
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//===----------------------------------------------------------------------===//
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// Subtraction
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
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def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SH(Y)?$")>;
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def : InstRW<[FXU], (instregex "SGR(K)?$")>;
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def : InstRW<[FXU], (instregex "SLFI$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
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def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
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def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
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def : InstRW<[FXU], (instregex "SLR(K)?$")>;
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def : InstRW<[FXU], (instregex "SR(K)?$")>;
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// Subtraction with borrow
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def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
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def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
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// Subtraction with sign extension (32 -> 64)
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def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "SGF$")>;
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def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "SGFR$")>;
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//===----------------------------------------------------------------------===//
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// AND
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
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def : InstRW<[FXU], (instregex "NGR(K)?$")>;
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def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
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def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
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def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
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def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
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def : InstRW<[FXU], (instregex "NILF(64)?$")>;
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def : InstRW<[FXU], (instregex "NILH(64)?$")>;
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def : InstRW<[FXU], (instregex "NILL(64)?$")>;
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def : InstRW<[FXU], (instregex "NR(K)?$")>;
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def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
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//===----------------------------------------------------------------------===//
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// OR
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
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def : InstRW<[FXU], (instregex "OGR(K)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
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def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
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def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
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def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
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def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
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def : InstRW<[FXU], (instregex "OILF(64)?$")>;
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def : InstRW<[FXU], (instregex "OILH(64)?$")>;
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def : InstRW<[FXU], (instregex "OILL(64)?$")>;
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def : InstRW<[FXU], (instregex "OR(K)?$")>;
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def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
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//===----------------------------------------------------------------------===//
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// XOR
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
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def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
|
|
def : InstRW<[FXU], (instregex "XIFMux$")>;
|
|
def : InstRW<[FXU], (instregex "XGR(K)?$")>;
|
|
def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
|
|
def : InstRW<[FXU], (instregex "XILF(64)?$")>;
|
|
def : InstRW<[FXU], (instregex "XR(K)?$")>;
|
|
def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Multiplication
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
|
|
def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
|
|
def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
|
|
def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
|
|
def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
|
|
def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
|
|
def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
|
|
def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
|
|
def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
|
|
def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Division and remainder
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
|
(instregex "DSG(F)?R$")>;
|
|
def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
|
|
(instregex "DSG(F)?$")>;
|
|
def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
|
(instregex "DL(G)?R$")>;
|
|
def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
|
(instregex "DL(G)?$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Shifts
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
|
|
def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
|
|
def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
|
|
def : InstRW<[FXU, Lat2], (instregex "SLA(K)?$")>;
|
|
|
|
// Rotate
|
|
def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
|
|
|
|
// Rotate and insert
|
|
def : InstRW<[FXU], (instregex "RISBG(32)?$")>;
|
|
def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
|
|
def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
|
|
def : InstRW<[FXU], (instregex "RISBMux$")>;
|
|
|
|
// Rotate and Select
|
|
def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Comparison
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
|
|
def : InstRW<[FXU], (instregex "C(F|H)I(Mux)?$")>;
|
|
def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
|
|
def : InstRW<[FXU], (instregex "C(G)?R$")>;
|
|
def : InstRW<[FXU], (instregex "CIH$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
|
|
def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
|
|
def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
|
|
def : InstRW<[FXU], (instregex "CLGR$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
|
|
def : InstRW<[FXU], (instregex "CLIH$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
|
|
def : InstRW<[FXU], (instregex "CLR$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
|
|
|
|
// Compare halfword
|
|
def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CH(Y|RL)?$")>;
|
|
def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CGH(RL)?$")>;
|
|
def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CHHSI$")>;
|
|
|
|
// Compare with sign extension (32 -> 64)
|
|
def : InstRW<[FXU, FXU, LSU, Lat6, Lat2, GroupAlone], (instregex "CGF(RL)?$")>;
|
|
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "CGFR$")>;
|
|
|
|
// Compare logical character
|
|
def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "CLC$")>;
|
|
|
|
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
|
|
|
|
// Test under mask
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
|
|
def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
|
|
def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
|
|
def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
|
|
def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
|
|
def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Prefetch
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : InstRW<[LSU, GroupAlone], (instregex "PFD(RL)?$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Atomic operations
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
|
|
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
|
|
|
|
// Test and set
|
|
def : InstRW<[FXU, LSU, Lat5, EndGroup], (instregex "TS$")>;
|
|
|
|
// Compare and swap
|
|
def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
|
|
|
|
// Compare double and swap
|
|
def : InstRW<[FXU, FXU, FXU, FXU, FXU, LSU, Lat10, GroupAlone],
|
|
(instregex "CDS(Y)?$")>;
|
|
def : InstRW<[FXU, FXU, FXU, FXU, FXU, FXU, LSU, LSU, Lat12, GroupAlone],
|
|
(instregex "CDSG$")>;
|
|
|
|
// Compare and swap and store
|
|
def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CSST$")>;
|
|
|
|
// Perform locked operation
|
|
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>;
|
|
|
|
// Load/store pair from/to quadword
|
|
def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>;
|
|
def : InstRW<[FXU, FXU, LSU, LSU, Lat6, GroupAlone], (instregex "STPQ$")>;
|
|
|
|
// Load pair disjoint
|
|
def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Access registers
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Extract/set/copy access register
|
|
def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
|
|
|
|
// Load address extended
|
|
def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
|
|
|
|
// Load/store access multiple (not modeled precisely)
|
|
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Program mask and addressing mode
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Insert Program Mask
|
|
def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
|
|
|
|
// Set Program Mask
|
|
def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
|
|
|
|
// Branch and link
|
|
def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
|
|
|
|
// Test addressing mode
|
|
def : InstRW<[FXU], (instregex "TAM$")>;
|
|
|
|
// Set addressing mode
|
|
def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
|
|
|
|
// Branch (and save) and set mode.
|
|
def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
|
|
def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Miscellaneous Instructions.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Find leftmost one
|
|
def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
|
|
|
|
// Population count
|
|
def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
|
|
|
|
// Extend
|
|
def : InstRW<[FXU], (instregex "AEXT128_64$")>;
|
|
def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
|
|
|
|
// String instructions
|
|
def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
|
|
|
|
// Move with key
|
|
def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
|
|
|
|
// Extract CPU Time
|
|
def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
|
|
|
|
// Execute
|
|
def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
|
|
|
|
// Program return
|
|
def : InstRW<[FXU, Lat30], (instregex "PR$")>;
|
|
|
|
// Inline assembly
|
|
def : InstRW<[FXU, LSU, Lat15], (instregex "STCK$")>;
|
|
def : InstRW<[FXU, LSU, Lat12], (instregex "STCKF$")>;
|
|
def : InstRW<[LSU, FXU, Lat5], (instregex "STCKE$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
|
|
def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
|
|
|
|
// Store real address
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// .insn directive instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// An "empty" sched-class will be assigned instead of the "invalid sched-class".
|
|
// getNumDecoderSlots() will then return 1 instead of 0.
|
|
def : InstRW<[], (instregex "Insn.*")>;
|
|
|
|
|
|
// ----------------------------- Floating point ----------------------------- //
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FP: Select instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
|
|
def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
|
|
def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FP: Move instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Load zero
|
|
def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
|
|
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
|
|
|
|
// Load
|
|
def : InstRW<[FXU], (instregex "LER$")>;
|
|
def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
|
|
def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
|
|
def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
|
|
|
|
// Load and Test
|
|
def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
|
|
def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
|
|
def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
|
|
(instregex "LTXBRCompare(_VecPseudo)?$")>;
|
|
|
|
// Copy sign
|
|
def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
|
|
def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FP: Load instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : InstRW<[LSU], (instregex "LE(Y)?$")>;
|
|
def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
|
|
def : InstRW<[LSU], (instregex "LX$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FP: Store instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
|
|
def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
|
|
def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FP: Conversion instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Load rounded
|
|
def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
|
|
def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
|
|
def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
|
|
|
|
// Load lengthened
|
|
def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
|
|
def : InstRW<[FPU], (instregex "LDEBR$")>;
|
|
def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
|
|
|
|
// Convert from fixed / logical
|
|
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A)?$")>;
|
|
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A)?$")>;
|
|
def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A)?$")>;
|
|
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
|
|
def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
|
|
def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
|
|
|
|
// Convert to fixed / logical
|
|
def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A)?$")>;
|
|
def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A)?$")>;
|
|
def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A)?$")>;
|
|
def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
|
|
def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
|
|
def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FP: Unary arithmetic
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Load Complement / Negative / Positive
|
|
def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
|
|
def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
|
|
def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
|
|
def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
|
|
def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
|
|
|
|
// Square root
|
|
def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
|
|
def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
|
|
|
|
// Load FP integer
|
|
def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
|
|
def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FP: Binary arithmetic
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Addition
|
|
def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
|
|
def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
|
|
|
|
// Subtraction
|
|
def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
|
|
def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
|
|
|
|
// Multiply
|
|
def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
|
|
def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
|
|
def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
|
|
|
|
// Multiply and add / subtract
|
|
def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
|
|
def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
|
|
def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
|
|
def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
|
|
|
|
// Division
|
|
def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
|
|
def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
|
|
def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// FP: Comparisons
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Compare
|
|
def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
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def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
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def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
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// Test Data Class
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def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
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def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
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//===----------------------------------------------------------------------===//
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// FP: Floating-point control register instructions
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "EFPC$")>;
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def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>;
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def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>;
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def : InstRW<[LSU, Lat3, GroupAlone], (instregex "STFPC$")>;
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def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>;
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def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
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def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>;
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}
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