mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 19:52:54 +01:00
9667127c14
The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
56 lines
1.9 KiB
C++
56 lines
1.9 KiB
C++
//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file implements an allocation order for virtual registers.
|
|
//
|
|
// The preferred allocation order for a virtual register depends on allocation
|
|
// hints and target hooks. The AllocationOrder class encapsulates all of that.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "AllocationOrder.h"
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
#include "llvm/CodeGen/RegisterClassInfo.h"
|
|
#include "llvm/CodeGen/VirtRegMap.h"
|
|
#include "llvm/Support/Debug.h"
|
|
#include "llvm/Support/raw_ostream.h"
|
|
|
|
using namespace llvm;
|
|
|
|
#define DEBUG_TYPE "regalloc"
|
|
|
|
// Compare VirtRegMap::getRegAllocPref().
|
|
AllocationOrder::AllocationOrder(unsigned VirtReg,
|
|
const VirtRegMap &VRM,
|
|
const RegisterClassInfo &RegClassInfo,
|
|
const LiveRegMatrix *Matrix)
|
|
: Pos(0), HardHints(false) {
|
|
const MachineFunction &MF = VRM.getMachineFunction();
|
|
const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
|
|
Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
|
|
if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix))
|
|
HardHints = true;
|
|
rewind();
|
|
|
|
LLVM_DEBUG({
|
|
if (!Hints.empty()) {
|
|
dbgs() << "hints:";
|
|
for (unsigned I = 0, E = Hints.size(); I != E; ++I)
|
|
dbgs() << ' ' << printReg(Hints[I], TRI);
|
|
dbgs() << '\n';
|
|
}
|
|
});
|
|
#ifndef NDEBUG
|
|
for (unsigned I = 0, E = Hints.size(); I != E; ++I)
|
|
assert(is_contained(Order, Hints[I]) &&
|
|
"Target hint is outside allocation order.");
|
|
#endif
|
|
}
|