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247 lines
6.8 KiB
Plaintext
247 lines
6.8 KiB
Plaintext
//===---------------------------------------------------------------------===//
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// Random ideas for the ARM backend (Thumb specific).
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//===---------------------------------------------------------------------===//
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* Add support for compiling functions in both ARM and Thumb mode, then taking
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the smallest.
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* Add support for compiling individual basic blocks in thumb mode, when in a
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larger ARM function. This can be used for presumed cold code, like paths
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to abort (failure path of asserts), EH handling code, etc.
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* Thumb doesn't have normal pre/post increment addressing modes, but you can
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load/store 32-bit integers with pre/postinc by using load/store multiple
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instrs with a single register.
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* Make better use of high registers r8, r10, r11, r12 (ip). Some variants of add
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and cmp instructions can use high registers. Also, we can use them as
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temporaries to spill values into.
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* In thumb mode, short, byte, and bool preferred alignments are currently set
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to 4 to accommodate ISA restriction (i.e. add sp, #imm, imm must be multiple
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of 4).
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//===---------------------------------------------------------------------===//
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Potential jumptable improvements:
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* If we know function size is less than (1 << 16) * 2 bytes, we can use 16-bit
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jumptable entries (e.g. (L1 - L2) >> 1). Or even smaller entries if the
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function is even smaller. This also applies to ARM.
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* Thumb jumptable codegen can improve given some help from the assembler. This
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is what we generate right now:
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.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
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LPCRELL0:
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mov r1, #PCRELV0
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add r1, pc
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ldr r0, [r0, r1]
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cpy pc, r0
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.align 2
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LJTI1_0_0:
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.long LBB1_3
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...
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Note there is another pc relative add that we can take advantage of.
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add r1, pc, #imm_8 * 4
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We should be able to generate:
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LPCRELL0:
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add r1, LJTI1_0_0
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ldr r0, [r0, r1]
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cpy pc, r0
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.align 2
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LJTI1_0_0:
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.long LBB1_3
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if the assembler can translate the add to:
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add r1, pc, #((LJTI1_0_0-(LPCRELL0+4))&0xfffffffc)
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Note the assembler also does something similar to constpool load:
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LPCRELL0:
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ldr r0, LCPI1_0
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=>
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ldr r0, pc, #((LCPI1_0-(LPCRELL0+4))&0xfffffffc)
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//===---------------------------------------------------------------------===//
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We compiles the following:
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define i16 @func_entry_2E_ce(i32 %i) {
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switch i32 %i, label %bb12.exitStub [
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i32 0, label %bb4.exitStub
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i32 1, label %bb9.exitStub
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i32 2, label %bb4.exitStub
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i32 3, label %bb4.exitStub
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i32 7, label %bb9.exitStub
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i32 8, label %bb.exitStub
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i32 9, label %bb9.exitStub
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]
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bb12.exitStub:
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ret i16 0
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bb4.exitStub:
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ret i16 1
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bb9.exitStub:
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ret i16 2
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bb.exitStub:
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ret i16 3
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}
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into:
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_func_entry_2E_ce:
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mov r2, #1
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lsl r2, r0
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cmp r0, #9
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bhi LBB1_4 @bb12.exitStub
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LBB1_1: @newFuncRoot
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mov r1, #13
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tst r2, r1
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bne LBB1_5 @bb4.exitStub
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LBB1_2: @newFuncRoot
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ldr r1, LCPI1_0
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tst r2, r1
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bne LBB1_6 @bb9.exitStub
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LBB1_3: @newFuncRoot
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mov r1, #1
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lsl r1, r1, #8
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tst r2, r1
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bne LBB1_7 @bb.exitStub
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LBB1_4: @bb12.exitStub
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mov r0, #0
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bx lr
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LBB1_5: @bb4.exitStub
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mov r0, #1
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bx lr
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LBB1_6: @bb9.exitStub
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mov r0, #2
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bx lr
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LBB1_7: @bb.exitStub
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mov r0, #3
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bx lr
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LBB1_8:
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.align 2
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LCPI1_0:
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.long 642
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gcc compiles to:
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cmp r0, #9
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@ lr needed for prologue
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bhi L2
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ldr r3, L11
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mov r2, #1
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mov r1, r2, asl r0
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ands r0, r3, r2, asl r0
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movne r0, #2
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bxne lr
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tst r1, #13
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beq L9
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L3:
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mov r0, r2
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bx lr
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L9:
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tst r1, #256
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movne r0, #3
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bxne lr
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L2:
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mov r0, #0
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bx lr
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L12:
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.align 2
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L11:
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.long 642
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GCC is doing a couple of clever things here:
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1. It is predicating one of the returns. This isn't a clear win though: in
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cases where that return isn't taken, it is replacing one condbranch with
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two 'ne' predicated instructions.
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2. It is sinking the shift of "1 << i" into the tst, and using ands instead of
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tst. This will probably require whole function isel.
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3. GCC emits:
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tst r1, #256
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we emit:
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mov r1, #1
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lsl r1, r1, #8
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tst r2, r1
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//===---------------------------------------------------------------------===//
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When spilling in thumb mode and the sp offset is too large to fit in the ldr /
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str offset field, we load the offset from a constpool entry and add it to sp:
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ldr r2, LCPI
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add r2, sp
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ldr r2, [r2]
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These instructions preserve the condition code which is important if the spill
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is between a cmp and a bcc instruction. However, we can use the (potentially)
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cheaper sequnce if we know it's ok to clobber the condition register.
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add r2, sp, #255 * 4
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add r2, #132
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ldr r2, [r2, #7 * 4]
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This is especially bad when dynamic alloca is used. The all fixed size stack
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objects are referenced off the frame pointer with negative offsets. See
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oggenc for an example.
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//===---------------------------------------------------------------------===//
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We are reserving R3 as a scratch register under thumb mode. So if it is live in
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to the function, we save / restore R3 to / from R12. Until register scavenging
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is done, we should save R3 to a high callee saved reg at emitPrologue time
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(when hasFP is true or stack size is large) and restore R3 from that register
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instead. This allows us to at least get rid of the save to r12 everytime it is
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used.
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//===---------------------------------------------------------------------===//
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Poor codegen test/CodeGen/ARM/select.ll f7:
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ldr r5, LCPI1_0
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LPC0:
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add r5, pc
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ldr r6, LCPI1_1
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ldr r2, LCPI1_2
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cpy r3, r6
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cpy lr, pc
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bx r5
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//===---------------------------------------------------------------------===//
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Make register allocator / spiller smarter so we can re-materialize "mov r, imm",
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etc. Almost all Thumb instructions clobber condition code.
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//===---------------------------------------------------------------------===//
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Add ldmia, stmia support.
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//===---------------------------------------------------------------------===//
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Thumb load / store address mode offsets are scaled. The values kept in the
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instruction operands are pre-scale values. This probably ought to be changed
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to avoid extra work when we convert Thumb2 instructions to Thumb1 instructions.
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//===---------------------------------------------------------------------===//
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We need to make (some of the) Thumb1 instructions predicable. That will allow
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shrinking of predicated Thumb2 instructions. To allow this, we need to be able
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to toggle the 's' bit since they do not set CPSR when they are inside IT blocks.
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//===---------------------------------------------------------------------===//
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Make use of hi register variants of cmp: tCMPhir / tCMPZhir.
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//===---------------------------------------------------------------------===//
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