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ec3a12595c
ARM counterpart to r248291: In the comparison failure block of a cmpxchg expansion, the initial ldrex/ldxr will not be followed by a matching strex/stxr. On ARM/AArch64, this unnecessarily ties up the execution monitor, which might have a negative performance impact on some uarchs. Instead, release the monitor in the failure block. The clrex instruction was designed for this: use it. Also see ARMARM v8-A B2.10.2: "Exclusive access instructions and Shareable memory locations". Differential Revision: http://reviews.llvm.org/D13033 llvm-svn: 248294
111 lines
3.8 KiB
LLVM
111 lines
3.8 KiB
LLVM
; RUN: opt -atomic-expand -S -mtriple=thumbv7s-apple-ios7.0 %s | FileCheck %s
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define i32 @test_cmpxchg_seq_cst(i32* %addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: @test_cmpxchg_seq_cst
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; Intrinsic for "dmb ishst" is then expected
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; CHECK: call void @llvm.arm.dmb(i32 10)
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; CHECK: br label %[[START:.*]]
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; CHECK: [[START]]:
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; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
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; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
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; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
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; CHECK: [[TRY_STORE]]:
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; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr)
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; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
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; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
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; CHECK: [[SUCCESS_BB]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[END:.*]]
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; CHECK: [[NO_STORE_BB]]:
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; CHECK: call void @llvm.arm.clrex()
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; CHECK: br label %[[FAILURE_BB]]
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; CHECK: [[FAILURE_BB]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[END]]
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; CHECK: [[END]]:
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; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
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; CHECK: ret i32 [[LOADED]]
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%pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
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%oldval = extractvalue { i32, i1 } %pair, 0
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ret i32 %oldval
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}
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define i1 @test_cmpxchg_weak_fail(i32* %addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: @test_cmpxchg_weak_fail
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; CHECK: call void @llvm.arm.dmb(i32 10)
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; CHECK: br label %[[START:.*]]
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; CHECK: [[START]]:
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; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
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; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
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; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
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; CHECK: [[TRY_STORE]]:
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; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr)
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; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
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; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
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; CHECK: [[SUCCESS_BB]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[END:.*]]
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; CHECK: [[NO_STORE_BB]]:
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; CHECK: call void @llvm.arm.clrex()
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; CHECK: br label %[[FAILURE_BB]]
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; CHECK: [[FAILURE_BB]]:
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; CHECK-NOT: dmb
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; CHECK: br label %[[END]]
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; CHECK: [[END]]:
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; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
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; CHECK: ret i1 [[SUCCESS]]
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%pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
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%oldval = extractvalue { i32, i1 } %pair, 1
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ret i1 %oldval
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}
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define i32 @test_cmpxchg_monotonic(i32* %addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: @test_cmpxchg_monotonic
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; CHECK-NOT: dmb
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; CHECK: br label %[[START:.*]]
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; CHECK: [[START]]:
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; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
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; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
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; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[NO_STORE_BB:.*]]
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; CHECK: [[TRY_STORE]]:
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; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* %addr)
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; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
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; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
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; CHECK: [[SUCCESS_BB]]:
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; CHECK-NOT: dmb
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; CHECK: br label %[[END:.*]]
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; CHECK: [[NO_STORE_BB]]:
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; CHECK: call void @llvm.arm.clrex()
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; CHECK: br label %[[FAILURE_BB]]
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; CHECK: [[FAILURE_BB]]:
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; CHECK-NOT: dmb
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; CHECK: br label %[[END]]
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; CHECK: [[END]]:
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; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
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; CHECK: ret i32 [[LOADED]]
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%pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new monotonic monotonic
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%oldval = extractvalue { i32, i1 } %pair, 0
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ret i32 %oldval
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}
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