Mehdi Amini 7d809bb14e Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer ... We can build it with -Werror=global-constructors now. This helps in situation where libSupport is embedded as a shared library, potential with dlopen/dlclose scenario, and when command-line parsing or other facilities may not be involved. Avoiding the implicit construction of these cl::opt can avoid double-registration issues and other kind of behavior. Reviewed By: lattner, jpienaar Differential Revision: https://reviews.llvm.org/D105959		2021-07-16 07:38:16 +00:00
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AsmParser	Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer	2021-07-16 07:38:16 +00:00
Disassembler
MCTargetDesc	[RISCV] Pass FeatureBitset by reference rather than by value. NFCI	2021-07-04 23:11:40 -07:00
TargetInfo
CMakeLists.txt	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCV.h	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCV.td
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCVFrameLowering.cpp	[RISCV] Avoid scalar outgoing argumetns overwriting vector frame objects.	2021-06-11 12:26:29 +08:00
RISCVFrameLowering.h
RISCVInsertVSETVLI.cpp	[RISCV] Remove extra character from a comment. NFC	2021-06-21 12:52:02 -07:00
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
RISCVInstrInfo.cpp	[RISCV] Permit larger RVV stacks and stack offsets	2021-06-25 07:17:33 +01:00
RISCVInstrInfo.h	Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.	2021-06-08 09:43:43 -07:00
RISCVInstrInfo.td	[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.	2021-07-13 09:46:21 -07:00
RISCVInstrInfoA.td
RISCVInstrInfoB.td	[RISCV] Prevent formation of shXadd(.uw) and add.uw if it prevents the use of addi.	2021-06-19 12:10:42 -07:00
RISCVInstrInfoC.td
RISCVInstrInfoD.td	[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno	2021-07-06 11:43:22 -07:00
RISCVInstrInfoF.td	[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno	2021-07-06 11:43:22 -07:00
RISCVInstrInfoM.td
RISCVInstrInfoV.td
RISCVInstrInfoVPseudos.td	[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.	2021-06-21 11:27:44 -07:00
RISCVInstrInfoVSDPatterns.td	[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.	2021-06-21 11:27:44 -07:00
RISCVInstrInfoVVLPatterns.td	[RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors.	2021-07-06 10:24:31 -07:00
RISCVInstrInfoZfh.td	[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno	2021-07-06 11:43:22 -07:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp	[RISCV] Add explicit copy to V0 in the masked vmsge(u).vx intrinsic handling.	2021-06-23 08:04:42 -07:00
RISCVISelDAGToDAG.h	[RISCV] Use bitfields to shrink the size of the vector load/store intrinsics to pseudo instruction lookup tables.	2021-06-07 17:57:51 -07:00
RISCVISelLowering.cpp	[RISCV] Fix the neutral element in vector 'fadd' reductions	2021-07-14 10:18:38 +01:00
RISCVISelLowering.h	[RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors.	2021-07-06 10:24:31 -07:00
RISCVLegalizerInfo.cpp	[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one	2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp	[RISCV] Reserve an emergency spill slot for any RVV spills	2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
RISCVRegisterInfo.td	[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.	2021-07-13 09:46:21 -07:00
RISCVSchedRocket.td
RISCVSchedSiFive7.td
RISCVSchedule.td
RISCVScheduleB.td
RISCVSubtarget.cpp
RISCVSubtarget.h	[RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.	2021-06-07 10:20:59 -07:00
RISCVSystemOperands.td	RISCV: add a few deprecated aliases for CSRs	2021-05-21 13:52:58 -07:00
RISCVTargetMachine.cpp	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
RISCVTargetTransformInfo.h	[RISCV] Don't enable Interleaved Access Vectorization	2021-06-18 12:32:30 +08:00