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51 lines
1.7 KiB
LLVM
51 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s
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; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
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; dependency) when it isn't dependent on last CPSR defining instruction.
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; rdar://8928208
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define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
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entry:
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; CHECK: t1:
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; CHECK: muls [[REG:(r[0-9]+)]], r2, r3
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; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r0, r1
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; CHECK-NEXT: muls r0, [[REG2]], [[REG]]
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%0 = mul nsw i32 %a, %b
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%1 = mul nsw i32 %c, %d
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%2 = mul nsw i32 %0, %1
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ret i32 %2
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}
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; Avoid partial CPSR dependency via loop backedge.
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; rdar://10357570
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define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
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entry:
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; CHECK: t2:
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%tobool7 = icmp eq i32* %ptr2, null
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br i1 %tobool7, label %while.end, label %while.body
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while.body:
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; CHECK: while.body
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; CHECK: mul r{{[0-9]+}}
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; CHECK-NOT: muls
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%ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
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%ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
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%0 = load i32* %ptr1.addr.09, align 4
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%arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1
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%1 = load i32* %arrayidx1, align 4
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%arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2
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%2 = load i32* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3
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%3 = load i32* %arrayidx4, align 4
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%add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4
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%mul = mul i32 %1, %0
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%mul5 = mul i32 %mul, %2
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%mul6 = mul i32 %mul5, %3
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store i32 %mul6, i32* %ptr2.addr.08, align 4
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%incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1
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%tobool = icmp eq i32* %incdec.ptr, null
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br i1 %tobool, label %while.end, label %while.body
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while.end:
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ret void
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}
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