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llvm-mirror/test/CodeGen/Mips/2010-07-20-Switch.ll
Akira Hatanaka 874523adc5 Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.

llvm-svn: 149668
2012-02-03 04:33:00 +00:00

62 lines
1.8 KiB
LLVM

; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s -check-prefix=STATIC-O32
; RUN: llc < %s -march=mips -relocation-model=pic | FileCheck %s -check-prefix=PIC-O32
; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=PIC-N64
define i32 @main() nounwind readnone {
entry:
%x = alloca i32, align 4 ; <i32*> [#uses=2]
store volatile i32 2, i32* %x, align 4
%0 = load volatile i32* %x, align 4 ; <i32> [#uses=1]
; STATIC-O32: lui $[[R0:[0-9]+]], %hi($JTI0_0)
; STATIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0)
; STATIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
; PIC-O32: lw $[[R0:[0-9]+]], %got($JTI0_0)
; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0)
; PIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
; PIC-N64: ld $[[R0:[0-9]+]], %got_page($JTI0_0)
; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($JTI0_0)
; PIC-N64: dsll ${{[0-9]+}}, ${{[0-9]+}}, 3
switch i32 %0, label %bb4 [
i32 0, label %bb5
i32 1, label %bb1
i32 2, label %bb2
i32 3, label %bb3
]
bb1: ; preds = %entry
ret i32 2
; CHECK: STATIC-O32: $BB0_2
bb2: ; preds = %entry
ret i32 0
bb3: ; preds = %entry
ret i32 3
bb4: ; preds = %entry
ret i32 4
bb5: ; preds = %entry
ret i32 1
}
; STATIC-O32: .align 2
; STATIC-O32: $JTI0_0:
; STATIC-O32: .4byte
; STATIC-O32: .4byte
; STATIC-O32: .4byte
; STATIC-O32: .4byte
; PIC-O32: .align 2
; PIC-O32: $JTI0_0:
; PIC-O32: .gpword
; PIC-O32: .gpword
; PIC-O32: .gpword
; PIC-O32: .gpword
; PIC-N64: .align 3
; PIC-N64: $JTI0_0:
; PIC-N64: .gpdword
; PIC-N64: .gpdword
; PIC-N64: .gpdword
; PIC-N64: .gpdword